// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.12.0.240.2
// Netlist written on Sun Feb 14 22:24:48 2021
//
// Verilog Description of module controller
//

module controller (sys_clk, sys_rst_n, DS18B20_bus, uart_rx_bus, uart_tx_bus, 
            OLED_bus, BEEP_bus, key_bus, sw) /* synthesis syn_module_defined=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(11[8:18])
    input sys_clk;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(12[19:26])
    input sys_rst_n;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(13[19:28])
    inout DS18B20_bus;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(15[19:30])
    input uart_rx_bus;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(18[21:32])
    output uart_tx_bus;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(19[21:32])
    output [4:0]OLED_bus;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(21[19:27])
    output BEEP_bus;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(23[19:27])
    input [3:0]key_bus;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(25[19:26])
    input [3:0]sw;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(27[18:20])
    
    wire sys_clk_c /* synthesis SET_AS_NETWORK=sys_clk_c, is_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(12[19:26])
    wire uart_clk /* synthesis is_clock=1, SET_AS_NETWORK=uart_clk */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(256[5:13])
    wire clk_1us /* synthesis SET_AS_NETWORK=clk_1us, is_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(368[14:21])
    wire clock /* synthesis SET_AS_NETWORK=clock, is_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(419[6:11])
    wire sys_clk_N_7 /* synthesis is_inv_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(44[11:27])
    
    wire GND_net, VCC_net, sys_rst_n_c, uart_rx_bus_c, uart_tx_bus_c, 
        OLED_bus_c_4, OLED_bus_c_3, OLED_bus_c_2, OLED_bus_c_1, OLED_bus_c_0, 
        BEEP_bus_c, key_bus_c_1, key_bus_c_0, beep_en_reg, beep_en_uart;
    wire [4:0]Beep_status_uart;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(44[11:27])
    
    wire DS18B20_rst, clock_flag;
    wire [5:0]sec;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(69[11:14])
    wire [3:0]hour_h;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(70[10:16])
    wire [3:0]hour_l;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(70[17:23])
    wire [3:0]min_h;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(70[24:29])
    wire [3:0]min_l;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(70[30:35])
    
    wire uart_en_R_0, uart_en_R_1;
    wire [7:0]usart_recieve_state;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(163[10:29])
    wire [7:0]usart_recieve_cnt;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(164[10:27])
    wire [5:0]sec_u;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(166[11:16])
    wire [3:0]hour_h_u;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(167[10:18])
    wire [3:0]hour_l_u;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(167[19:27])
    wire [3:0]min_h_u;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(167[28:35])
    wire [3:0]min_l_u;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(167[36:43])
    
    wire time_set_flag, time_set_ready_flag;
    wire [31:0]usart_send_state;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(245[11:27])
    wire [31:0]usart_send_cnt;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(246[11:25])
    wire [15:0]uart_cnt;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(255[11:19])
    
    wire uart_en_w, uart_en_R;
    wire [7:0]uart_data_w;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(332[11:22])
    wire [7:0]uart_data_R;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(333[13:24])
    wire [19:0]temp_data;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(372[17:26])
    
    wire sign;
    wire [19:0]temperature_data;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(430[11:27])
    wire [3:0]temp_h;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(441[10:16])
    wire [3:0]temp_l;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(441[17:23])
    wire [3:0]temp_p;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(441[24:30])
    
    wire DS18B20_rst_N_367, n42, n43, n44, n45, n46, n70, n71, 
        n72, n73, clock_flag_N_372, sys_clk_N_7_enable_28, n160, n161, 
        n162, n163, n165, n170, n171, n172, n173, n16676, n180, 
        n181, n182, n183, n184, n185, n4921, n4920, n4919;
    wire [3:0]min_l_3__N_195;
    
    wire clock_flag_N_368, n288, n289, n290, n291, n292, n293, 
        n294, n295, n27645, n154, n7, n153, n456, n31, n569, 
        n4907, n4905;
    wire [7:0]usart_recieve_state_7__N_222;
    
    wire n25285, n26533, n29612, time_set_flag_N_377, uart_clk_N_390, 
        n28609, n15689, n4901, n4900, n4899, n26877, n1128, n1130, 
        n25348, sys_clk_N_7_enable_15;
    wire [31:0]usart_send_state_31__N_281;
    
    wire usart_send_state_31__N_277, uart_en_w_N_392, n24;
    wire [7:0]uart_data_w_7__N_345;
    
    wire sys_clk_N_7_enable_50, sys_clk_N_7_enable_48, sys_clk_N_7_enable_45, 
        sys_clk_N_7_enable_39, rx_flag, n28608, n29610, n8, n29609, 
        sys_clk_N_7_enable_33, n147, n150, n26871, n146, n29606, 
        n2426, n7_adj_1806, n107, n27579, n31_adj_1807, dq_N_756, 
        n2, n7_adj_1808, n3, n28980, n29563;
    wire [7:0]char_reg;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(52[17:25])
    wire [4:0]cnt_main;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(53[12:20])
    wire [15:0]cnt_adj_1865;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(54[35:38])
    
    wire n26855, clock_enable_33, n29562, n846, n1011, n1012, n1013, 
        n1014, n1015, n1016, n1017, n1389, n1390, n1391, n1392, 
        n1393, n1394, n1395, n1767, n1768, n1769, n1770, n1771, 
        n1772, n1773, n2145, n2146, n2147, n2148, n2149, n2150, 
        n2151, n2523, n2524, n2525, n2526, n2527, n2528, n2529, 
        sys_clk_N_7_enable_54, sys_clk_c_enable_47, n27417, n10, n161_adj_1809, 
        n160_adj_1810, n159, n158, n27585, n28947, n155, n29601, 
        clk_1us_enable_43, n2749, n27879, n2735, n2733, n21256, 
        n27857, n28607, n162_adj_1811, n164, n157, n151, n27849, 
        n7921, n148, n22, n22_adj_1812, n14, n22_adj_1813, n2054, 
        n152, n7918, clock_enable_21, n2053, n2052, n2049, n2048, 
        n145, n144, n143, n142, n141, n165_adj_1814, n140, n139, 
        n138, n137, n136, n135, n134, n156, n15254, n27404, 
        n29595, sys_clk_N_7_enable_8, n4, n27628, n16, n27414, n18, 
        n13, n27583, n27646, n56, n27577, n26287, n14_adj_1815, 
        n27576, n55, n54, n29729, n52, n27580, n27587, n14_adj_1816, 
        n7_adj_1817, n163_adj_1818, n50, n149, n18_adj_1819, n27578, 
        n47, n26027, n14_adj_1820, n27597, n26265, clk_1us_enable_8, 
        n23732, n43_adj_1821, n26523, n2_adj_1822, n26551, n8566, 
        n70_adj_1823, n71_adj_1824, n72_adj_1825, n73_adj_1826, n74, 
        n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, 
        n85, n22_adj_1827, n28, n26525, n31_adj_1828, DS18B20_bus_out, 
        n22_adj_1829, n24_adj_1830, n28_adj_1831, n30, n31_adj_1832, 
        n14_adj_1833, n15384, n27541, n8_adj_1834, n24937, n29418, 
        n29417, n27581, n24935, n48, n6, n75_adj_1835, n46_adj_1836, 
        n27453, n24967, n24966, n29584, n44_adj_1837, n40, n29583, 
        n29582, n24965, n36, n24964, n35, n10_adj_1838, n29557, 
        n29548, n24963, n24934, n24962, n24936, n25055, n25054, 
        n24961, n32, n28789, n28788, n28787, n25053, n27426, n24960, 
        n8_adj_1839, n25052, n15687, n25051, n25050, n25049, n25048, 
        n29576, n29575, sys_clk_c_enable_77, clock_enable_24, n29573, 
        n25047, n29572, n8730, n25046, n25045, n29710, n25044, 
        n29571, n25043, n25042, n25041, n25040, clk_1us_enable_11, 
        sys_clk_N_7_enable_57, n16625, n21002, n26, n11, n17, n28004, 
        n29695, n4_adj_1840, n29694, n29688, n26493, n29684, n27584, 
        n16624, n28744, n29680, n29678, n27630, n18822, n29676, 
        n29675, n29672, n29669, n29668, sys_clk_N_7_enable_23, n28732, 
        n6_adj_1841, n5, n27779, n27598, n29661, n29660, clock_enable_27, 
        n21236, n29656, n29655, n8_adj_1842, n29654, n27629, n27586, 
        n29649, n6_adj_1843, n27415, n29641, n29731, n29640, n28034, 
        n28032, n29636, n28030, n29634, n27644, n29631, n29629, 
        n29628, n29627, n7_adj_1844, n29730, n27963, n20, n18_adj_1845, 
        n8_adj_1846, n29564, n14_adj_1847, n29614;
    
    VHI i2 (.Z(VCC_net));
    INV i23429 (.A(sys_clk_c), .Z(sys_clk_N_7));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(12[19:26])
    LUT4 i2660_2_lut (.A(sec[1]), .B(sec[0]), .Z(n46)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(97[16:24])
    defparam i2660_2_lut.init = 16'h6666;
    LUT4 i19_4_lut (.A(uart_data_R[7]), .B(usart_recieve_state[7]), .C(n29609), 
         .D(n29548), .Z(n26855)) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(201[18] 239[16])
    defparam i19_4_lut.init = 16'hca0a;
    LUT4 i8_1_lut (.A(time_set_flag), .Z(n2733)) /* synthesis lut_function=(!(A)) */ ;
    defparam i8_1_lut.init = 16'h5555;
    IB sys_rst_n_pad (.I(sys_rst_n), .O(sys_rst_n_c));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(13[19:28])
    FD1P3AX usart_recieve_cnt_i0_i0 (.D(n25348), .SP(sys_clk_N_7_enable_23), 
            .CK(sys_clk_N_7), .Q(usart_recieve_cnt[0]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam usart_recieve_cnt_i0_i0.GSR = "ENABLED";
    FD1S3AX i75_254 (.D(clock_flag_N_368), .CK(clock), .Q(clock_flag));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(82[10] 124[8])
    defparam i75_254.GSR = "ENABLED";
    FD1S3AX uart_en_R_0_256 (.D(uart_en_R), .CK(sys_clk_c), .Q(uart_en_R_0));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(140[10] 143[8])
    defparam uart_en_R_0_256.GSR = "ENABLED";
    FD1S3AX uart_en_R_1_257 (.D(uart_en_R_0), .CK(sys_clk_c), .Q(uart_en_R_1));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(140[10] 143[8])
    defparam uart_en_R_1_257.GSR = "ENABLED";
    LUT4 i1_2_lut_rep_384 (.A(sys_rst_n_c), .B(usart_recieve_state[5]), 
         .Z(n29660)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i1_2_lut_rep_384.init = 16'h8888;
    LUT4 i2_3_lut_4_lut (.A(sys_rst_n_c), .B(usart_recieve_state[5]), .C(n29688), 
         .D(n26), .Z(n27453)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i2_3_lut_4_lut.init = 16'h8000;
    LUT4 i1_2_lut_rep_385 (.A(usart_recieve_cnt[1]), .B(usart_recieve_cnt[0]), 
         .Z(n29661)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i1_2_lut_rep_385.init = 16'h2222;
    FD1P3AX uart_data_w_i0_i7 (.D(uart_data_w_7__N_345[7]), .SP(clk_1us_enable_8), 
            .CK(clk_1us), .Q(uart_data_w[7]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(268[10] 323[8])
    defparam uart_data_w_i0_i7.GSR = "DISABLED";
    LUT4 i1_2_lut_3_lut (.A(usart_recieve_cnt[1]), .B(usart_recieve_cnt[0]), 
         .C(n75_adj_1835), .Z(sys_clk_N_7_enable_48)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i1_2_lut_3_lut.init = 16'h2020;
    FD1P3AX uart_data_w_i0_i6 (.D(uart_data_w_7__N_345[6]), .SP(clk_1us_enable_8), 
            .CK(clk_1us), .Q(uart_data_w[6]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(268[10] 323[8])
    defparam uart_data_w_i0_i6.GSR = "DISABLED";
    FD1P3AX uart_data_w_i0_i5 (.D(uart_data_w_7__N_345[5]), .SP(clk_1us_enable_8), 
            .CK(clk_1us), .Q(uart_data_w[5]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(268[10] 323[8])
    defparam uart_data_w_i0_i5.GSR = "DISABLED";
    FD1P3AX uart_data_w_i0_i4 (.D(uart_data_w_7__N_345[4]), .SP(clk_1us_enable_8), 
            .CK(clk_1us), .Q(uart_data_w[4]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(268[10] 323[8])
    defparam uart_data_w_i0_i4.GSR = "DISABLED";
    FD1P3AX uart_data_w_i0_i3 (.D(uart_data_w_7__N_345[3]), .SP(clk_1us_enable_8), 
            .CK(clk_1us), .Q(uart_data_w[3]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(268[10] 323[8])
    defparam uart_data_w_i0_i3.GSR = "DISABLED";
    FD1P3AX uart_data_w_i0_i2 (.D(uart_data_w_7__N_345[2]), .SP(clk_1us_enable_8), 
            .CK(clk_1us), .Q(uart_data_w[2]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(268[10] 323[8])
    defparam uart_data_w_i0_i2.GSR = "DISABLED";
    FD1P3AX uart_data_w_i0_i1 (.D(uart_data_w_7__N_345[1]), .SP(clk_1us_enable_8), 
            .CK(clk_1us), .Q(uart_data_w[1]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(268[10] 323[8])
    defparam uart_data_w_i0_i1.GSR = "DISABLED";
    FD1P3AX temp_h_i0_i0 (.D(uart_data_R[0]), .SP(sys_clk_N_7_enable_15), 
            .CK(sys_clk_N_7), .Q(temp_h[0]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam temp_h_i0_i0.GSR = "ENABLED";
    FD1P3AX temp_l_i0_i0 (.D(uart_data_R[0]), .SP(sys_clk_N_7_enable_50), 
            .CK(sys_clk_N_7), .Q(temp_l[0]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam temp_l_i0_i0.GSR = "ENABLED";
    FD1P3AX temp_p_i0_i0 (.D(uart_data_R[0]), .SP(sys_clk_N_7_enable_48), 
            .CK(sys_clk_N_7), .Q(temp_p[0]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam temp_p_i0_i0.GSR = "ENABLED";
    FD1P3AX hour_l_u_i0_i0 (.D(uart_data_R[0]), .SP(sys_clk_N_7_enable_45), 
            .CK(sys_clk_N_7), .Q(hour_l_u[0]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam hour_l_u_i0_i0.GSR = "DISABLED";
    FD1P3AX hour_h_u_i0_i0 (.D(uart_data_R[4]), .SP(sys_clk_N_7_enable_45), 
            .CK(sys_clk_N_7), .Q(hour_h_u[0]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam hour_h_u_i0_i0.GSR = "DISABLED";
    FD1P3AX min_l_u_i0_i0 (.D(uart_data_R[0]), .SP(sys_clk_N_7_enable_39), 
            .CK(sys_clk_N_7), .Q(min_l_u[0]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam min_l_u_i0_i0.GSR = "DISABLED";
    FD1P3AX i190_263 (.D(time_set_flag_N_377), .SP(sys_clk_N_7_enable_8), 
            .CK(sys_clk_N_7), .Q(time_set_flag));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i190_263.GSR = "ENABLED";
    FD1P3AX min_h_u_i0_i0 (.D(uart_data_R[4]), .SP(sys_clk_N_7_enable_39), 
            .CK(sys_clk_N_7), .Q(min_h_u[0]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam min_h_u_i0_i0.GSR = "DISABLED";
    FD1P3AX sec_u_i0_i0 (.D(uart_data_R[0]), .SP(sys_clk_N_7_enable_33), 
            .CK(sys_clk_N_7), .Q(sec_u[0]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam sec_u_i0_i0.GSR = "DISABLED";
    FD1P3AX temperature_data__i1 (.D(temp_data[0]), .SP(clock_enable_21), 
            .CK(clock), .Q(temperature_data[0]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(431[8] 440[4])
    defparam temperature_data__i1.GSR = "DISABLED";
    FD1S3AX uart_clk_272 (.D(uart_clk_N_390), .CK(clk_1us), .Q(uart_clk));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(257[8] 261[4])
    defparam uart_clk_272.GSR = "DISABLED";
    FD1S3AX uart_en_w_273 (.D(uart_en_w_N_392), .CK(uart_clk), .Q(uart_en_w));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(268[10] 323[8])
    defparam uart_en_w_273.GSR = "ENABLED";
    ds18b20_dri u1_ds18b20_dri (.clk_1us(clk_1us), .DS18B20_rst(DS18B20_rst), 
            .dq_N_756(dq_N_756), .sign(sign), .\temp_data[0] (temp_data[0]), 
            .DS18B20_bus_out(DS18B20_bus_out), .GND_net(GND_net), .\temp_data[10] (temp_data[10]), 
            .\temp_data[9] (temp_data[9]), .\temp_data[8] (temp_data[8]), 
            .\temp_data[7] (temp_data[7]), .\temp_data[6] (temp_data[6]), 
            .\temp_data[5] (temp_data[5]), .\temp_data[4] (temp_data[4]), 
            .\temp_data[3] (temp_data[3]), .\temp_data[2] (temp_data[2]), 
            .\temp_data[1] (temp_data[1]), .n8566(n8566)) /* synthesis syn_module_defined=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(376[13] 384[2])
    ROM128X1A mux_562_Mux_32 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n1017)) /* synthesis initstate=0x0000090417F5797C00A800000000E8A8 */ ;
    defparam mux_562_Mux_32.initval = 128'h0000090417F5797C00A800000000E8A8;
    FD1P3IX usart_recieve_state_i0_i0 (.D(n569), .SP(sys_clk_N_7_enable_57), 
            .CD(n18822), .CK(sys_clk_N_7), .Q(usart_recieve_state[0]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam usart_recieve_state_i0_i0.GSR = "ENABLED";
    FD1P3AX sec_i0_i5 (.D(n180), .SP(clock_enable_33), .CK(clock), .Q(sec[5]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(82[10] 124[8])
    defparam sec_i0_i5.GSR = "ENABLED";
    FD1P3AX sec_i0_i4 (.D(n181), .SP(clock_enable_33), .CK(clock), .Q(sec[4]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(82[10] 124[8])
    defparam sec_i0_i4.GSR = "ENABLED";
    FD1P3AX sec_i0_i3 (.D(n182), .SP(clock_enable_33), .CK(clock), .Q(sec[3]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(82[10] 124[8])
    defparam sec_i0_i3.GSR = "ENABLED";
    ROM128X1A mux_562_Mux_30 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n1389)) /* synthesis initstate=0x04A8927EACAA96B54BEF426800007BEF */ ;
    defparam mux_562_Mux_30.initval = 128'h04A8927EACAA96B54BEF426800007BEF;
    ROM128X1A mux_562_Mux_33 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n1016)) /* synthesis initstate=0x0000090403EFF9FD832500600000FB25 */ ;
    defparam mux_562_Mux_33.initval = 128'h0000090403EFF9FD832500600000FB25;
    FD1P3AX uart_data_w_i0_i0 (.D(uart_data_w_7__N_345[0]), .SP(clk_1us_enable_8), 
            .CK(clk_1us), .Q(uart_data_w[0]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(268[10] 323[8])
    defparam uart_data_w_i0_i0.GSR = "DISABLED";
    ROM128X1A mux_562_Mux_39 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n1011)) /* synthesis initstate=0x050D6D04950D7976000400200000EC04 */ ;
    defparam mux_562_Mux_39.initval = 128'h050D6D04950D7976000400200000EC04;
    ROM128X1A mux_562_Mux_37 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n1012)) /* synthesis initstate=0x00A5E93E05A7FDF7016980700000FD69 */ ;
    defparam mux_562_Mux_37.initval = 128'h00A5E93E05A7FDF7016980700000FD69;
    ROM128X1A mux_562_Mux_22 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n1767)) /* synthesis initstate=0x0478923EBE7A96BD836F405000007B6F */ ;
    defparam mux_562_Mux_22.initval = 128'h0478923EBE7A96BD836F405000007B6F;
    LUT4 i17753_3_lut (.A(hour_h[1]), .B(hour_l[1]), .C(cnt_main[0]), 
         .Z(n11)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(53[12:20])
    defparam i17753_3_lut.init = 16'hcaca;
    VLO i1 (.Z(GND_net));
    ROM128X1A mux_562_Mux_14 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n2145)) /* synthesis initstate=0x04989E3EACA892A5117F11080000597F */ ;
    defparam mux_562_Mux_14.initval = 128'h04989E3EACA892A5117F11080000597F;
    ROM128X1A mux_562_Mux_6 (.AD0(n29584), .AD1(n29564), .AD2(n846), .AD3(n29563), 
            .AD4(n29583), .AD5(n29562), .AD6(n29582), .DO0(n2523)) /* synthesis initstate=0x07226192950679A20004004000004404 */ ;
    defparam mux_562_Mux_6.initval = 128'h07226192950679A20004004000004404;
    LUT4 mux_53_i1_4_lut (.A(sec[0]), .B(sec_u[0]), .C(time_set_flag), 
         .D(n7918), .Z(n185)) /* synthesis lut_function=(A (B (C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(96[10] 124[8])
    defparam mux_53_i1_4_lut.init = 16'hc0c5;
    ROM128X1A mux_562_Mux_24 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n1395)) /* synthesis initstate=0x001010012C1F82FDC3AD02CC0000FBAD */ ;
    defparam mux_562_Mux_24.initval = 128'h001010012C1F82FDC3AD02CC0000FBAD;
    ROM128X1A mux_562_Mux_25 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n1394)) /* synthesis initstate=0x00100040580020020C42001C00000442 */ ;
    defparam mux_562_Mux_25.initval = 128'h00100040580020020C42001C00000442;
    ROM128X1A mux_562_Mux_26 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n1393)) /* synthesis initstate=0x041BA2FA090040083C3001AC00000030 */ ;
    defparam mux_562_Mux_26.initval = 128'h041BA2FA090040083C3001AC00000030;
    ROM128X1A mux_562_Mux_27 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n1392)) /* synthesis initstate=0x011441441A0D096503402D580000CB40 */ ;
    defparam mux_562_Mux_27.initval = 128'h011441441A0D096503402D580000CB40;
    ROM128X1A mux_562_Mux_28 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n1391)) /* synthesis initstate=0x001808620D0000023C91810800000491 */ ;
    defparam mux_562_Mux_28.initval = 128'h001808620D0000023C91810800000491;
    ROM128X1A mux_562_Mux_35 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n1014)) /* synthesis initstate=0x02EFE9FC00E7F9F6105128000000FC51 */ ;
    defparam mux_562_Mux_35.initval = 128'h02EFE9FC00E7F9F6105128000000FC51;
    ROM128X1A mux_562_Mux_36 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n1013)) /* synthesis initstate=0x02E7E9BC10E7F9F7215104480000FD51 */ ;
    defparam mux_562_Mux_36.initval = 128'h02E7E9BC10E7F9F7215104480000FD51;
    FD1P3AX temp_l_i0_i1 (.D(uart_data_R[1]), .SP(sys_clk_N_7_enable_50), 
            .CK(sys_clk_N_7), .Q(temp_l[1]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam temp_l_i0_i1.GSR = "ENABLED";
    FD1P3AX temp_h_i0_i3 (.D(uart_data_R[3]), .SP(sys_clk_N_7_enable_15), 
            .CK(sys_clk_N_7), .Q(temp_h[3]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam temp_h_i0_i3.GSR = "ENABLED";
    PFUMX i22726 (.BLUT(n14), .ALUT(n29417), .C0(cnt_adj_1865[4]), .Z(n29418));
    LUT4 i22213_4_lut (.A(key_bus_c_1), .B(time_set_flag), .C(key_bus_c_0), 
         .D(n28030), .Z(clock_enable_27)) /* synthesis lut_function=(A (B+((D)+!C))) */ ;
    defparam i22213_4_lut.init = 16'haa8a;
    FD1P3AX min_l_2263__i0 (.D(n31_adj_1832), .SP(clock_enable_24), .CK(clock), 
            .Q(min_l[0]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(101[22:33])
    defparam min_l_2263__i0.GSR = "ENABLED";
    FD1P3AX sec_i0_i2 (.D(n183), .SP(clock_enable_33), .CK(clock), .Q(sec[2]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(82[10] 124[8])
    defparam sec_i0_i2.GSR = "ENABLED";
    LUT4 i18893_2_lut (.A(min_l[1]), .B(min_l[0]), .Z(n24_adj_1830)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(101[22:33])
    defparam i18893_2_lut.init = 16'h6666;
    FD1P3AX sec_i0_i1 (.D(n184), .SP(clock_enable_33), .CK(clock), .Q(sec[1]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(82[10] 124[8])
    defparam sec_i0_i1.GSR = "ENABLED";
    FD1P3AX sec_i0_i0 (.D(n185), .SP(clock_enable_33), .CK(clock), .Q(sec[0]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(82[10] 124[8])
    defparam sec_i0_i0.GSR = "ENABLED";
    FD1P3AX hour_l_2264__i0 (.D(n31_adj_1828), .SP(clock_enable_27), .CK(clock), 
            .Q(hour_l[0]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(112[22:35])
    defparam hour_l_2264__i0.GSR = "ENABLED";
    LUT4 i14397_2_lut (.A(min_l_u[1]), .B(time_set_flag), .Z(min_l_3__N_195[1])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(96[10] 124[8])
    defparam i14397_2_lut.init = 16'h8888;
    FD1S3AX uart_cnt_2265__i0 (.D(n85), .CK(clk_1us), .Q(uart_cnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265__i0.GSR = "DISABLED";
    ROM128X1A mux_562_Mux_16 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n1773)) /* synthesis initstate=0x000012407C1F86FF83EF00D20000FFEF */ ;
    defparam mux_562_Mux_16.initval = 128'h000012407C1F86FF83EF00D20000FFEF;
    ROM128X1A mux_562_Mux_17 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n1772)) /* synthesis initstate=0x00001001001002085C120F9200000012 */ ;
    defparam mux_562_Mux_17.initval = 128'h00001001001002085C120F9200000012;
    ROM128X1A mux_562_Mux_18 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n1771)) /* synthesis initstate=0x041FD7BE10102A082C2A0C5A0000002A */ ;
    defparam mux_562_Mux_18.initval = 128'h041FD7BE10102A082C2A0C5A0000002A;
    ROM128X1A mux_562_Mux_19 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n1770)) /* synthesis initstate=0x00003A40059D63E503C3AC320000CBC3 */ ;
    defparam mux_562_Mux_19.initval = 128'h00003A40059D63E503C3AC320000CBC3;
    ROM128X1A mux_562_Mux_20 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n1769)) /* synthesis initstate=0x0588322212960A0BAC160C5800000416 */ ;
    defparam mux_562_Mux_20.initval = 128'h0588322212960A0BAC160C5800000416;
    ROM128X1A mux_562_Mux_21 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n1768)) /* synthesis initstate=0x02831A80029002085C025F1200000002 */ ;
    defparam mux_562_Mux_21.initval = 128'h02831A80029002085C025F1200000002;
    LUT4 i2716_3_lut_4_lut (.A(min_h[1]), .B(n29612), .C(min_h[2]), .D(min_h[3]), 
         .Z(n70)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(106[21:33])
    defparam i2716_3_lut_4_lut.init = 16'h7f80;
    IB uart_rx_bus_pad (.I(uart_rx_bus), .O(uart_rx_bus_c));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(18[21:32])
    LUT4 i21880_4_lut (.A(n15687), .B(n29629), .C(n27849), .D(clock_flag_N_372), 
         .Z(n28030)) /* synthesis lut_function=(A (B+(C+(D)))) */ ;
    defparam i21880_4_lut.init = 16'haaa8;
    LUT4 hour_l_2264_mux_6_i1_4_lut (.A(hour_l_u[0]), .B(hour_l[0]), .C(n2735), 
         .D(time_set_flag), .Z(n31_adj_1828)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+(D)))+!A (B+!(C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(112[22:35])
    defparam hour_l_2264_mux_6_i1_4_lut.init = 16'h3a30;
    FD1P3AX temp_h_i0_i2 (.D(uart_data_R[2]), .SP(sys_clk_N_7_enable_15), 
            .CK(sys_clk_N_7), .Q(temp_h[2]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam temp_h_i0_i2.GSR = "ENABLED";
    IB sys_clk_pad (.I(sys_clk), .O(sys_clk_c));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(12[19:26])
    ROM128X1A mux_562_Mux_29 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n1390)) /* synthesis initstate=0x075300C0184000000484403800000084 */ ;
    defparam mux_562_Mux_29.initval = 128'h075300C0184000000484403800000084;
    LUT4 i14387_2_lut (.A(min_l_u[3]), .B(time_set_flag), .Z(min_l_3__N_195[3])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(96[10] 124[8])
    defparam i14387_2_lut.init = 16'h8888;
    OB BEEP_bus_pad (.I(BEEP_bus_c), .O(BEEP_bus));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(23[19:27])
    FD1P3AX temp_h_i0_i1 (.D(uart_data_R[1]), .SP(sys_clk_N_7_enable_15), 
            .CK(sys_clk_N_7), .Q(temp_h[1]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam temp_h_i0_i1.GSR = "ENABLED";
    LUT4 i4_4_lut (.A(usart_recieve_state[6]), .B(usart_recieve_state[2]), 
         .C(usart_recieve_state[1]), .D(usart_recieve_state[5]), .Z(n10)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i4_4_lut.init = 16'hfffe;
    ROM128X1A mux_562_Mux_0 (.AD0(n29584), .AD1(n29564), .AD2(n846), .AD3(n29563), 
            .AD4(n29583), .AD5(n29562), .AD6(n29582), .DO0(n2529)) /* synthesis initstate=0x0000001017F86D6000A800200000C0A8 */ ;
    defparam mux_562_Mux_0.initval = 128'h0000001017F86D6000A800200000C0A8;
    ROM128X1A mux_562_Mux_1 (.AD0(n29584), .AD1(n29564), .AD2(n846), .AD3(n29563), 
            .AD4(n29583), .AD5(n29562), .AD6(n29582), .DO0(n2528)) /* synthesis initstate=0x0000005007E7E1858385803000001B85 */ ;
    defparam mux_562_Mux_1.initval = 128'h0000005007E7E1858385803000001B85;
    ROM128X1A mux_562_Mux_2 (.AD0(n29584), .AD1(n29564), .AD2(n846), .AD3(n29563), 
            .AD4(n29583), .AD5(n29562), .AD6(n29582), .DO0(n2527)) /* synthesis initstate=0x07E2009052E7E117A305040800002F05 */ ;
    defparam mux_562_Mux_2.initval = 128'h07E2009052E7E117A305040800002F05;
    ROM128X1A mux_562_Mux_3 (.AD0(n29584), .AD1(n29564), .AD2(n846), .AD3(n29563), 
            .AD4(n29583), .AD5(n29562), .AD6(n29582), .DO0(n2526)) /* synthesis initstate=0x02E7E1B600E2E19B4221280000002621 */ ;
    defparam mux_562_Mux_3.initval = 128'h02E7E1B600E2E19B4221280000002621;
    ROM128X1A mux_562_Mux_4 (.AD0(n29584), .AD1(n29564), .AD2(n846), .AD3(n29563), 
            .AD4(n29583), .AD5(n29562), .AD6(n29582), .DO0(n2525)) /* synthesis initstate=0x02E3E1B610EAE1972379045800002F79 */ ;
    defparam mux_562_Mux_4.initval = 128'h02E3E1B610EAE1972379045800002F79;
    ROM128X1A mux_562_Mux_5 (.AD0(n29584), .AD1(n29564), .AD2(n846), .AD3(n29563), 
            .AD4(n29583), .AD5(n29562), .AD6(n29582), .DO0(n2524)) /* synthesis initstate=0x02BAE19E01A8E1870169002000001D69 */ ;
    defparam mux_562_Mux_5.initval = 128'h02BAE19E01A8E1870169002000001D69;
    LUT4 DS18B20_rst_I_0_2_lut (.A(DS18B20_rst), .B(sys_rst_n_c), .Z(DS18B20_rst_N_367)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(60[10] 65[8])
    defparam DS18B20_rst_I_0_2_lut.init = 16'h6666;
    OB OLED_bus_pad_0 (.I(OLED_bus_c_0), .O(OLED_bus[0]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(21[19:27])
    OB OLED_bus_pad_1 (.I(OLED_bus_c_1), .O(OLED_bus[1]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(21[19:27])
    OB OLED_bus_pad_2 (.I(OLED_bus_c_2), .O(OLED_bus[2]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(21[19:27])
    OB OLED_bus_pad_3 (.I(OLED_bus_c_3), .O(OLED_bus[3]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(21[19:27])
    ROM128X1A mux_562_Mux_8 (.AD0(n29584), .AD1(n29564), .AD2(n846), .AD3(n29563), 
            .AD4(n29583), .AD5(n29562), .AD6(n29582), .DO0(n2151)) /* synthesis initstate=0x000004402C1F86E593FD012C0000DBFD */ ;
    defparam mux_562_Mux_8.initval = 128'h000004402C1F86E593FD012C0000DBFD;
    LUT4 i14646_2_lut_rep_396 (.A(key_bus_c_0), .B(key_bus_c_1), .Z(n29672)) /* synthesis lut_function=(A (B)) */ ;
    defparam i14646_2_lut_rep_396.init = 16'h8888;
    ROM128X1A mux_562_Mux_9 (.AD0(n29584), .AD1(n29564), .AD2(n846), .AD3(n29563), 
            .AD4(n29583), .AD5(n29562), .AD6(n29582), .DO0(n2150)) /* synthesis initstate=0x0000000070002C120018007C00002418 */ ;
    defparam mux_562_Mux_9.initval = 128'h0000000070002C120018007C00002418;
    ROM128X1A mux_562_Mux_10 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n2149)) /* synthesis initstate=0x040DEDAF2500040060B1820C000000B1 */ ;
    defparam mux_562_Mux_10.initval = 128'h040DEDAF2500040060B1820C000000B1;
    ROM128X1A mux_562_Mux_11 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n2148)) /* synthesis initstate=0x05020410320D05EC835C2E180000CB5C */ ;
    defparam mux_562_Mux_11.initval = 128'h05020410320D05EC835C2E180000CB5C;
    ROM128X1A mux_562_Mux_12 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n2147)) /* synthesis initstate=0x000A0422210044036010022800000410 */ ;
    defparam mux_562_Mux_12.initval = 128'h000A0422210044036010022800000410;
    ROM128X1A mux_562_Mux_13 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n2146)) /* synthesis initstate=0x0361048030460C100210105800002210 */ ;
    defparam mux_562_Mux_13.initval = 128'h0361048030460C100210105800002210;
    FD1P3AX min_h_i0_i0 (.D(n173), .SP(clock_enable_33), .CK(clock), .Q(min_h[0]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(82[10] 124[8])
    defparam min_h_i0_i0.GSR = "ENABLED";
    FD1P3AX Beep_status_uart_i0_i0 (.D(uart_data_R[0]), .SP(sys_clk_N_7_enable_54), 
            .CK(sys_clk_N_7), .Q(Beep_status_uart[0]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam Beep_status_uart_i0_i0.GSR = "DISABLED";
    LUT4 i15122_3_lut_4_lut (.A(key_bus_c_0), .B(key_bus_c_1), .C(time_set_flag), 
         .D(n15687), .Z(clock_enable_33)) /* synthesis lut_function=(A (B (C+(D)))) */ ;
    defparam i15122_3_lut_4_lut.init = 16'h8880;
    ROM128X1A mux_562_Mux_34 (.AD0(n29584), .AD1(n29564), .AD2(n846), 
            .AD3(n29563), .AD4(n29583), .AD5(n29562), .AD6(n29582), 
            .DO0(n1015)) /* synthesis initstate=0x07F5690452EFF9FE236104580000FF61 */ ;
    defparam mux_562_Mux_34.initval = 128'h07F5690452EFF9FE236104580000FF61;
    LUT4 mux_336_Mux_2_i22_4_lut_3_lut (.A(cnt_adj_1865[1]), .B(cnt_adj_1865[2]), 
         .C(cnt_adj_1865[0]), .Z(n22_adj_1812)) /* synthesis lut_function=(A (B)+!A !(B+!(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(117[20] 120[14])
    defparam mux_336_Mux_2_i22_4_lut_3_lut.init = 16'h9898;
    FD1P3AX usart_send_state_FSM__i1 (.D(n8730), .SP(clk_1us_enable_11), 
            .CK(clk_1us), .Q(usart_send_state[1]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(269[9] 322[16])
    defparam usart_send_state_FSM__i1.GSR = "ENABLED";
    LUT4 i3_4_lut (.A(n15689), .B(uart_data_R[0]), .C(uart_data_R[1]), 
         .D(n15384), .Z(n18_adj_1819)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(191[16:34])
    defparam i3_4_lut.init = 16'hffef;
    LUT4 usart_recieve_state_7__I_0_297_i10_2_lut_rep_399 (.A(usart_recieve_state[2]), 
         .B(usart_recieve_state[3]), .Z(n29675)) /* synthesis lut_function=((B)+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(96[13:45])
    defparam usart_recieve_state_7__I_0_297_i10_2_lut_rep_399.init = 16'hdddd;
    LUT4 i1_3_lut (.A(clock_flag_N_372), .B(key_bus_c_0), .C(n27414), 
         .Z(n2735)) /* synthesis lut_function=(A ((C)+!B)+!A !(B)) */ ;
    defparam i1_3_lut.init = 16'hb3b3;
    LUT4 cnt_2__bdd_4_lut_23349 (.A(cnt_adj_1865[2]), .B(cnt_adj_1865[4]), 
         .C(cnt_adj_1865[1]), .D(cnt_adj_1865[3]), .Z(n28947)) /* synthesis lut_function=(!(A (B+!(C))+!A (B (C)+!B !((D)+!C)))) */ ;
    defparam cnt_2__bdd_4_lut_23349.init = 16'h3525;
    LUT4 i1_2_lut_rep_352_3_lut (.A(hour_l[1]), .B(hour_l[2]), .C(hour_l[3]), 
         .Z(n29628)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(112[22:35])
    defparam i1_2_lut_rep_352_3_lut.init = 16'hfefe;
    LUT4 i1_2_lut (.A(uart_data_R[4]), .B(uart_data_R[2]), .Z(n15689)) /* synthesis lut_function=(A+!(B)) */ ;
    defparam i1_2_lut.init = 16'hbbbb;
    LUT4 i1_2_lut_3_lut_4_lut (.A(hour_l[1]), .B(hour_l[2]), .C(n15687), 
         .D(hour_l[3]), .Z(n43_adj_1821)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(112[22:35])
    defparam i1_2_lut_3_lut_4_lut.init = 16'hffef;
    LUT4 i1_2_lut_rep_353_3_lut (.A(hour_l[1]), .B(hour_l[2]), .C(hour_l[3]), 
         .Z(n29629)) /* synthesis lut_function=(A (C)+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(112[22:35])
    defparam i1_2_lut_rep_353_3_lut.init = 16'he0e0;
    LUT4 i1_2_lut_3_lut_4_lut_adj_348 (.A(hour_l[1]), .B(hour_l[2]), .C(hour_h[3]), 
         .D(hour_l[3]), .Z(n5)) /* synthesis lut_function=(!(A (C+!(D))+!A ((C+!(D))+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(112[22:35])
    defparam i1_2_lut_3_lut_4_lut_adj_348.init = 16'h0e00;
    LUT4 i2638_3_lut_rep_400 (.A(min_l[1]), .B(min_l[3]), .C(min_l[2]), 
         .Z(n29676)) /* synthesis lut_function=(A (B)+!A (B (C))) */ ;
    defparam i2638_3_lut_rep_400.init = 16'hc8c8;
    OB OLED_bus_pad_4 (.I(OLED_bus_c_4), .O(OLED_bus[4]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(21[19:27])
    LUT4 i2696_2_lut_rep_336_4_lut (.A(min_l[1]), .B(min_l[3]), .C(min_l[2]), 
         .D(min_h[0]), .Z(n29612)) /* synthesis lut_function=(A (B (D))+!A (B (C (D)))) */ ;
    defparam i2696_2_lut_rep_336_4_lut.init = 16'hc800;
    LUT4 i2694_2_lut_4_lut (.A(min_l[1]), .B(min_l[3]), .C(min_l[2]), 
         .D(min_h[0]), .Z(n73)) /* synthesis lut_function=(!(A (B (D)+!B !(D))+!A (B (C (D)+!C !(D))+!B !(D)))) */ ;
    defparam i2694_2_lut_4_lut.init = 16'h37c8;
    LUT4 mux_145_i1_4_lut (.A(uart_data_R[0]), .B(usart_recieve_state[0]), 
         .C(n29609), .D(n3), .Z(n569)) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(201[18] 239[16])
    defparam mux_145_i1_4_lut.init = 16'hca0a;
    LUT4 i1_4_lut (.A(n29601), .B(n29634), .C(usart_recieve_state[1]), 
         .D(n29688), .Z(n3)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i1_4_lut.init = 16'h8000;
    OB uart_tx_bus_pad (.I(uart_tx_bus_c), .O(uart_tx_bus));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(19[21:32])
    LUT4 i1_2_lut_rep_402 (.A(usart_recieve_cnt[3]), .B(usart_recieve_cnt[4]), 
         .Z(n29678)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i1_2_lut_rep_402.init = 16'heeee;
    LUT4 i2_2_lut_rep_355_3_lut (.A(usart_recieve_cnt[3]), .B(usart_recieve_cnt[4]), 
         .C(usart_recieve_cnt[2]), .Z(n29631)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i2_2_lut_rep_355_3_lut.init = 16'hfefe;
    LUT4 i1_2_lut_3_lut_4_lut_adj_349 (.A(usart_recieve_cnt[3]), .B(usart_recieve_cnt[4]), 
         .C(n18_adj_1819), .D(usart_recieve_cnt[2]), .Z(n6)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;
    defparam i1_2_lut_3_lut_4_lut_adj_349.init = 16'h0010;
    LUT4 i1_2_lut_rep_404 (.A(usart_recieve_cnt[0]), .B(usart_recieve_cnt[1]), 
         .Z(n29680)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_rep_404.init = 16'h8888;
    LUT4 i1_2_lut_3_lut_4_lut_adj_350 (.A(usart_recieve_cnt[0]), .B(usart_recieve_cnt[1]), 
         .C(n29595), .D(usart_recieve_state[4]), .Z(n7_adj_1817)) /* synthesis lut_function=(!(A (B+!(C (D)))+!A !(C (D)))) */ ;
    defparam i1_2_lut_3_lut_4_lut_adj_350.init = 16'h7000;
    LUT4 cnt_0__bdd_4_lut_22951 (.A(cnt_adj_1865[4]), .B(cnt_adj_1865[3]), 
         .C(cnt_adj_1865[1]), .D(cnt_adj_1865[2]), .Z(n28980)) /* synthesis lut_function=(!(A (C+(D))+!A (B (C (D))+!B !(C (D)+!C !(D))))) */ ;
    defparam cnt_0__bdd_4_lut_22951.init = 16'h144f;
    LUT4 i1_2_lut_rep_408 (.A(uart_data_R[4]), .B(uart_data_R[2]), .Z(n29684)) /* synthesis lut_function=((B)+!A) */ ;
    defparam i1_2_lut_rep_408.init = 16'hdddd;
    FD1P3AX hour_h_i0_i0 (.D(n163), .SP(clock_enable_33), .CK(clock), 
            .Q(hour_h[0]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(82[10] 124[8])
    defparam hour_h_i0_i0.GSR = "ENABLED";
    LUT4 i1_3_lut_rep_364_4_lut (.A(uart_data_R[4]), .B(uart_data_R[2]), 
         .C(uart_data_R[1]), .D(n15384), .Z(n29640)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ;
    defparam i1_3_lut_rep_364_4_lut.init = 16'hfffd;
    LUT4 i14909_2_lut_2_lut_3_lut (.A(cnt_adj_1865[1]), .B(cnt_adj_1865[2]), 
         .C(cnt_adj_1865[0]), .Z(n14)) /* synthesis lut_function=(!(A (C)+!A ((C)+!B))) */ ;
    defparam i14909_2_lut_2_lut_3_lut.init = 16'h0e0e;
    LUT4 mux_336_Mux_3_i30_4_lut_3_lut_4_lut (.A(cnt_adj_1865[1]), .B(cnt_adj_1865[2]), 
         .C(cnt_adj_1865[3]), .D(cnt_adj_1865[0]), .Z(n21256)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (C (D)))) */ ;
    defparam mux_336_Mux_3_i30_4_lut_3_lut_4_lut.init = 16'hfee0;
    LUT4 i1_3_lut_4_lut (.A(cnt_adj_1865[0]), .B(cnt_adj_1865[1]), .C(cnt_adj_1865[2]), 
         .D(cnt_adj_1865[3]), .Z(n4)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;
    defparam i1_3_lut_4_lut.init = 16'hfe00;
    LUT4 mux_336_Mux_1_i22_3_lut_3_lut_4_lut_3_lut (.A(cnt_adj_1865[0]), .B(cnt_adj_1865[1]), 
         .C(cnt_adj_1865[2]), .Z(n22)) /* synthesis lut_function=(!(A (B+(C))+!A (B (C)+!B !(C)))) */ ;
    defparam mux_336_Mux_1_i22_3_lut_3_lut_4_lut_3_lut.init = 16'h1616;
    LUT4 i1_2_lut_rep_412 (.A(usart_recieve_state[7]), .B(usart_recieve_state[6]), 
         .Z(n29688)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i1_2_lut_rep_412.init = 16'h4444;
    LUT4 i1_2_lut_rep_351_3_lut (.A(usart_recieve_state[7]), .B(usart_recieve_state[6]), 
         .C(usart_recieve_state[1]), .Z(n29627)) /* synthesis lut_function=(!(A+((C)+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i1_2_lut_rep_351_3_lut.init = 16'h0404;
    LUT4 i3_4_lut_adj_351 (.A(uart_data_R[5]), .B(uart_data_R[7]), .C(uart_data_R[3]), 
         .D(uart_data_R[6]), .Z(n15384)) /* synthesis lut_function=((B+(C+!(D)))+!A) */ ;
    defparam i3_4_lut_adj_351.init = 16'hfdff;
    LUT4 i305_1_lut_rep_418 (.A(usart_send_state_31__N_281[1]), .Z(n29694)) /* synthesis lut_function=(!(A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(308[22] 310[20])
    defparam i305_1_lut_rep_418.init = 16'h5555;
    LUT4 i1_2_lut_2_lut (.A(usart_send_state_31__N_281[1]), .B(sys_clk_c_enable_77), 
         .Z(n16624)) /* synthesis lut_function=((B)+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(308[22] 310[20])
    defparam i1_2_lut_2_lut.init = 16'hdddd;
    LUT4 i1_2_lut_2_lut_adj_352 (.A(usart_send_state_31__N_281[1]), .B(usart_send_state[1]), 
         .Z(n2426)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(308[22] 310[20])
    defparam i1_2_lut_2_lut_adj_352.init = 16'h4444;
    LUT4 i2662_2_lut_rep_419 (.A(sec[1]), .B(sec[0]), .Z(n29695)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(97[16:24])
    defparam i2662_2_lut_rep_419.init = 16'h8888;
    LUT4 i2674_2_lut_3_lut_4_lut (.A(sec[1]), .B(sec[0]), .C(sec[3]), 
         .D(sec[2]), .Z(n44)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(97[16:24])
    defparam i2674_2_lut_3_lut_4_lut.init = 16'h78f0;
    LUT4 i21705_4_lut (.A(n29628), .B(hour_h[2]), .C(n6_adj_1843), .D(hour_h[3]), 
         .Z(n27849)) /* synthesis lut_function=(A (B+(C+(D)))) */ ;
    defparam i21705_4_lut.init = 16'haaa8;
    LUT4 i2669_2_lut_rep_365_3_lut (.A(sec[1]), .B(sec[0]), .C(sec[2]), 
         .Z(n29641)) /* synthesis lut_function=(A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(97[16:24])
    defparam i2669_2_lut_rep_365_3_lut.init = 16'h8080;
    LUT4 i1_2_lut_rep_330_4_lut (.A(n15384), .B(uart_data_R[1]), .C(n29684), 
         .D(uart_data_R[0]), .Z(n29606)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(224[28:46])
    defparam i1_2_lut_rep_330_4_lut.init = 16'hfffe;
    CCU2D uart_cnt_2265_add_4_13 (.A0(uart_cnt[11]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(uart_cnt[12]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24965), .COUT(n24966), .S0(n74), .S1(n73_adj_1826));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265_add_4_13.INIT0 = 16'hfaaa;
    defparam uart_cnt_2265_add_4_13.INIT1 = 16'hfaaa;
    defparam uart_cnt_2265_add_4_13.INJECT1_0 = "NO";
    defparam uart_cnt_2265_add_4_13.INJECT1_1 = "NO";
    CCU2D add_88_3 (.A0(usart_recieve_cnt[1]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(usart_recieve_cnt[2]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24934), .COUT(n24935), .S0(n294), .S1(n293));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(207[82:104])
    defparam add_88_3.INIT0 = 16'h5aaa;
    defparam add_88_3.INIT1 = 16'h5aaa;
    defparam add_88_3.INJECT1_0 = "NO";
    defparam add_88_3.INJECT1_1 = "NO";
    CCU2D uart_cnt_2265_add_4_11 (.A0(uart_cnt[9]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(uart_cnt[10]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24964), .COUT(n24965), .S0(n76), .S1(n75));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265_add_4_11.INIT0 = 16'hfaaa;
    defparam uart_cnt_2265_add_4_11.INIT1 = 16'hfaaa;
    defparam uart_cnt_2265_add_4_11.INJECT1_0 = "NO";
    defparam uart_cnt_2265_add_4_11.INJECT1_1 = "NO";
    LUT4 i1_4_lut_adj_353 (.A(n27415), .B(n2_adj_1822), .C(n29655), .D(key_bus_c_0), 
         .Z(n26523)) /* synthesis lut_function=(A+(B (C+(D))+!B !((D)+!C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(112[22:35])
    defparam i1_4_lut_adj_353.init = 16'heefa;
    FD1P3AX usart_recieve_cnt_i0_i7 (.D(n26027), .SP(sys_clk_N_7_enable_23), 
            .CK(sys_clk_N_7), .Q(usart_recieve_cnt[7]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam usart_recieve_cnt_i0_i7.GSR = "ENABLED";
    CCU2D uart_cnt_2265_add_4_9 (.A0(uart_cnt[7]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(uart_cnt[8]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24963), .COUT(n24964), .S0(n78), .S1(n77));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265_add_4_9.INIT0 = 16'hfaaa;
    defparam uart_cnt_2265_add_4_9.INIT1 = 16'hfaaa;
    defparam uart_cnt_2265_add_4_9.INJECT1_0 = "NO";
    defparam uart_cnt_2265_add_4_9.INJECT1_1 = "NO";
    CCU2D add_88_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(usart_recieve_cnt[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .COUT(n24934), .S1(n295));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(207[82:104])
    defparam add_88_1.INIT0 = 16'hF000;
    defparam add_88_1.INIT1 = 16'h5555;
    defparam add_88_1.INJECT1_0 = "NO";
    defparam add_88_1.INJECT1_1 = "NO";
    CCU2D uart_cnt_2265_add_4_7 (.A0(uart_cnt[5]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(uart_cnt[6]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24962), .COUT(n24963), .S0(n80), .S1(n79));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265_add_4_7.INIT0 = 16'hfaaa;
    defparam uart_cnt_2265_add_4_7.INIT1 = 16'hfaaa;
    defparam uart_cnt_2265_add_4_7.INJECT1_0 = "NO";
    defparam uart_cnt_2265_add_4_7.INJECT1_1 = "NO";
    LUT4 i1_2_lut_adj_354 (.A(hour_l_u[1]), .B(time_set_flag), .Z(n2_adj_1822)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(112[22:35])
    defparam i1_2_lut_adj_354.init = 16'h8888;
    LUT4 i2667_2_lut_3_lut (.A(sec[1]), .B(sec[0]), .C(sec[2]), .Z(n45)) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(97[16:24])
    defparam i2667_2_lut_3_lut.init = 16'h7878;
    FD1P3AX usart_recieve_cnt_i0_i6 (.D(n26265), .SP(sys_clk_N_7_enable_23), 
            .CK(sys_clk_N_7), .Q(usart_recieve_cnt[6]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam usart_recieve_cnt_i0_i6.GSR = "ENABLED";
    FD1P3AX usart_recieve_cnt_i0_i5 (.D(n26287), .SP(sys_clk_N_7_enable_23), 
            .CK(sys_clk_N_7), .Q(usart_recieve_cnt[5]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam usart_recieve_cnt_i0_i5.GSR = "ENABLED";
    FD1P3AX usart_recieve_cnt_i0_i4 (.D(n26551), .SP(sys_clk_N_7_enable_23), 
            .CK(sys_clk_N_7), .Q(usart_recieve_cnt[4]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam usart_recieve_cnt_i0_i4.GSR = "ENABLED";
    FD1P3AX usart_recieve_cnt_i0_i3 (.D(n26493), .SP(sys_clk_N_7_enable_23), 
            .CK(sys_clk_N_7), .Q(usart_recieve_cnt[3]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam usart_recieve_cnt_i0_i3.GSR = "ENABLED";
    FD1P3AX usart_recieve_cnt_i0_i2 (.D(n26533), .SP(sys_clk_N_7_enable_23), 
            .CK(sys_clk_N_7), .Q(usart_recieve_cnt[2]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam usart_recieve_cnt_i0_i2.GSR = "ENABLED";
    FD1P3AX usart_recieve_cnt_i0_i1 (.D(n25285), .SP(sys_clk_N_7_enable_23), 
            .CK(sys_clk_N_7), .Q(usart_recieve_cnt[1]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam usart_recieve_cnt_i0_i1.GSR = "ENABLED";
    FD1P3AX usart_recieve_state_i0_i6 (.D(usart_recieve_state_7__N_222[6]), 
            .SP(sys_clk_N_7_enable_57), .CK(sys_clk_N_7), .Q(usart_recieve_state[6]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam usart_recieve_state_i0_i6.GSR = "ENABLED";
    FD1P3AX usart_recieve_state_i0_i5 (.D(usart_recieve_state_7__N_222[5]), 
            .SP(sys_clk_N_7_enable_57), .CK(sys_clk_N_7), .Q(usart_recieve_state[5]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam usart_recieve_state_i0_i5.GSR = "ENABLED";
    FD1P3AX usart_recieve_state_i0_i2 (.D(usart_recieve_state_7__N_222[2]), 
            .SP(sys_clk_N_7_enable_57), .CK(sys_clk_N_7), .Q(usart_recieve_state[2]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam usart_recieve_state_i0_i2.GSR = "ENABLED";
    FD1P3AX usart_recieve_state_i0_i1 (.D(usart_recieve_state_7__N_222[1]), 
            .SP(sys_clk_N_7_enable_57), .CK(sys_clk_N_7), .Q(usart_recieve_state[1]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam usart_recieve_state_i0_i1.GSR = "ENABLED";
    CCU2D add_88_9 (.A0(usart_recieve_cnt[7]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n24937), .S0(n288));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(207[82:104])
    defparam add_88_9.INIT0 = 16'h5aaa;
    defparam add_88_9.INIT1 = 16'h0000;
    defparam add_88_9.INJECT1_0 = "NO";
    defparam add_88_9.INJECT1_1 = "NO";
    FD1P3AX beep_en_uart_269 (.D(n29640), .SP(sys_clk_N_7_enable_28), .CK(sys_clk_N_7), 
            .Q(beep_en_uart));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam beep_en_uart_269.GSR = "DISABLED";
    CCU2D uart_cnt_2265_add_4_5 (.A0(uart_cnt[3]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(uart_cnt[4]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24961), .COUT(n24962), .S0(n82), .S1(n81));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265_add_4_5.INIT0 = 16'hfaaa;
    defparam uart_cnt_2265_add_4_5.INIT1 = 16'hfaaa;
    defparam uart_cnt_2265_add_4_5.INJECT1_0 = "NO";
    defparam uart_cnt_2265_add_4_5.INJECT1_1 = "NO";
    FD1P3AX beep_en_reg_247 (.D(beep_en_uart), .SP(sys_rst_n_c), .CK(sys_clk_c), 
            .Q(beep_en_reg));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(48[10] 51[8])
    defparam beep_en_reg_247.GSR = "DISABLED";
    LUT4 i2_2_lut (.A(hour_h[1]), .B(hour_h[0]), .Z(n6_adj_1843)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(70[10:16])
    defparam i2_2_lut.init = 16'heeee;
    BB DS18B20_bus_pad (.I(dq_N_756), .T(n8566), .B(DS18B20_bus), .O(DS18B20_bus_out));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(167[1] 313[4])
    LUT4 i3_4_lut_adj_355 (.A(n15687), .B(n29629), .C(time_set_flag), 
         .D(n27849), .Z(n27414)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;
    defparam i3_4_lut_adj_355.init = 16'h0002;
    LUT4 i16_4_lut_4_lut (.A(uart_data_R[4]), .B(uart_data_R[2]), .C(uart_data_R[1]), 
         .D(uart_data_R[0]), .Z(n8_adj_1834)) /* synthesis lut_function=(A (B+(C))+!A (((D)+!C)+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(333[13:24])
    defparam i16_4_lut_4_lut.init = 16'hfdbd;
    LUT4 cnt_0__bdd_3_lut_22698 (.A(cnt_adj_1865[0]), .B(cnt_adj_1865[1]), 
         .C(cnt_adj_1865[2]), .Z(n28788)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
    defparam cnt_0__bdd_3_lut_22698.init = 16'h4040;
    LUT4 i17747_4_lut (.A(hour_h[1]), .B(hour_h_u[1]), .C(time_set_flag), 
         .D(n43_adj_1821), .Z(n162)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(168[5:18])
    defparam i17747_4_lut.init = 16'hc0ca;
    LUT4 cnt_0__bdd_4_lut_22483 (.A(cnt_adj_1865[0]), .B(cnt_adj_1865[3]), 
         .C(cnt_adj_1865[1]), .D(cnt_adj_1865[2]), .Z(n28787)) /* synthesis lut_function=(!(A (B+(C+!(D)))+!A (B+(C (D))))) */ ;
    defparam cnt_0__bdd_4_lut_22483.init = 16'h0311;
    LUT4 min_l_2__bdd_4_lut_then_3_lut (.A(min_l[2]), .B(min_l[0]), .C(min_l[1]), 
         .Z(n29730)) /* synthesis lut_function=(!(A (B (C))+!A !(B (C)))) */ ;
    defparam min_l_2__bdd_4_lut_then_3_lut.init = 16'h6a6a;
    LUT4 min_l_2__bdd_4_lut_else_3_lut (.A(time_set_flag), .B(min_l_u[2]), 
         .Z(n29729)) /* synthesis lut_function=(A (B)) */ ;
    defparam min_l_2__bdd_4_lut_else_3_lut.init = 16'h8888;
    LUT4 mux_53_i6_4_lut (.A(n42), .B(sec_u[5]), .C(time_set_flag), .D(n7918), 
         .Z(n180)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(96[10] 124[8])
    defparam mux_53_i6_4_lut.init = 16'hc0ca;
    LUT4 i17737_4_lut (.A(hour_h[2]), .B(hour_h_u[2]), .C(time_set_flag), 
         .D(n43_adj_1821), .Z(n161)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(168[5:18])
    defparam i17737_4_lut.init = 16'hc0ca;
    LUT4 i4_4_lut_adj_356 (.A(n7_adj_1844), .B(usart_recieve_state[6]), 
         .C(n29656), .D(usart_recieve_state[1]), .Z(n15687)) /* synthesis lut_function=(A+((C+!(D))+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i4_4_lut_adj_356.init = 16'hfbff;
    LUT4 i22259_2_lut_rep_293 (.A(uart_clk), .B(n31_adj_1807), .Z(clk_1us_enable_11)) /* synthesis lut_function=(!(A+(B))) */ ;
    defparam i22259_2_lut_rep_293.init = 16'h1111;
    LUT4 i17735_4_lut (.A(hour_h[3]), .B(hour_h_u[3]), .C(time_set_flag), 
         .D(n43_adj_1821), .Z(n160)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(168[5:18])
    defparam i17735_4_lut.init = 16'hc0ca;
    CCU2D usart_send_cnt_2266_add_4_33 (.A0(usart_send_cnt[31]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25055), .S0(n134));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266_add_4_33.INIT0 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_33.INIT1 = 16'h0000;
    defparam usart_send_cnt_2266_add_4_33.INJECT1_0 = "NO";
    defparam usart_send_cnt_2266_add_4_33.INJECT1_1 = "NO";
    LUT4 i1_2_lut_3_lut_adj_357 (.A(uart_clk), .B(n31_adj_1807), .C(sys_rst_n_c), 
         .Z(clk_1us_enable_8)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;
    defparam i1_2_lut_3_lut_adj_357.init = 16'h1010;
    LUT4 i3_4_lut_adj_358 (.A(sec[5]), .B(sec[3]), .C(sec[4]), .D(sec[2]), 
         .Z(n15254)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i3_4_lut_adj_358.init = 16'h8000;
    CCU2D usart_send_cnt_2266_add_4_31 (.A0(usart_send_cnt[29]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(usart_send_cnt[30]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n25054), .COUT(n25055), .S0(n136), 
          .S1(n135));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266_add_4_31.INIT0 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_31.INIT1 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_31.INJECT1_0 = "NO";
    defparam usart_send_cnt_2266_add_4_31.INJECT1_1 = "NO";
    CCU2D usart_send_cnt_2266_add_4_29 (.A0(usart_send_cnt[27]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(usart_send_cnt[28]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n25053), .COUT(n25054), .S0(n138), 
          .S1(n137));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266_add_4_29.INIT0 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_29.INIT1 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_29.INJECT1_0 = "NO";
    defparam usart_send_cnt_2266_add_4_29.INJECT1_1 = "NO";
    LUT4 mux_53_i5_4_lut (.A(n43), .B(sec_u[4]), .C(time_set_flag), .D(n7918), 
         .Z(n181)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(96[10] 124[8])
    defparam mux_53_i5_4_lut.init = 16'hc0ca;
    LUT4 i22267_3_lut_rep_285_4_lut (.A(uart_clk), .B(n31_adj_1807), .C(clock_flag), 
         .D(usart_send_state[0]), .Z(clk_1us_enable_43)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;
    defparam i22267_3_lut_rep_285_4_lut.init = 16'h0100;
    LUT4 mux_336_Mux_1_i31_3_lut_4_lut (.A(n28980), .B(cnt_adj_1865[0]), 
         .C(n29576), .D(char_reg[1]), .Z(n2054)) /* synthesis lut_function=(A (B (C (D))+!B ((D)+!C))+!A (C (D))) */ ;
    defparam mux_336_Mux_1_i31_3_lut_4_lut.init = 16'hf202;
    LUT4 mux_336_Mux_2_i31_3_lut_4_lut (.A(n28947), .B(cnt_adj_1865[0]), 
         .C(n29576), .D(char_reg[2]), .Z(n2053)) /* synthesis lut_function=(A (B (C (D))+!B ((D)+!C))+!A (C (D))) */ ;
    defparam mux_336_Mux_2_i31_3_lut_4_lut.init = 16'hf202;
    LUT4 mux_53_i4_4_lut (.A(n44), .B(sec_u[3]), .C(time_set_flag), .D(n7918), 
         .Z(n182)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(96[10] 124[8])
    defparam mux_53_i4_4_lut.init = 16'hc0ca;
    FD1P3AX temperature_data__i11 (.D(temp_data[10]), .SP(clock_enable_21), 
            .CK(clock), .Q(temperature_data[10]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(431[8] 440[4])
    defparam temperature_data__i11.GSR = "DISABLED";
    FD1P3AX temperature_data__i10 (.D(temp_data[9]), .SP(clock_enable_21), 
            .CK(clock), .Q(temperature_data[9]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(431[8] 440[4])
    defparam temperature_data__i10.GSR = "DISABLED";
    FD1P3AX temperature_data__i9 (.D(temp_data[8]), .SP(clock_enable_21), 
            .CK(clock), .Q(temperature_data[8]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(431[8] 440[4])
    defparam temperature_data__i9.GSR = "DISABLED";
    FD1P3AX temperature_data__i8 (.D(temp_data[7]), .SP(clock_enable_21), 
            .CK(clock), .Q(temperature_data[7]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(431[8] 440[4])
    defparam temperature_data__i8.GSR = "DISABLED";
    FD1P3AX temperature_data__i7 (.D(temp_data[6]), .SP(clock_enable_21), 
            .CK(clock), .Q(temperature_data[6]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(431[8] 440[4])
    defparam temperature_data__i7.GSR = "DISABLED";
    FD1P3AX temperature_data__i6 (.D(temp_data[5]), .SP(clock_enable_21), 
            .CK(clock), .Q(temperature_data[5]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(431[8] 440[4])
    defparam temperature_data__i6.GSR = "DISABLED";
    FD1P3AX temperature_data__i5 (.D(temp_data[4]), .SP(clock_enable_21), 
            .CK(clock), .Q(temperature_data[4]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(431[8] 440[4])
    defparam temperature_data__i5.GSR = "DISABLED";
    FD1P3AX temperature_data__i4 (.D(temp_data[3]), .SP(clock_enable_21), 
            .CK(clock), .Q(temperature_data[3]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(431[8] 440[4])
    defparam temperature_data__i4.GSR = "DISABLED";
    FD1P3AX temperature_data__i3 (.D(temp_data[2]), .SP(clock_enable_21), 
            .CK(clock), .Q(temperature_data[2]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(431[8] 440[4])
    defparam temperature_data__i3.GSR = "DISABLED";
    FD1P3AX temperature_data__i2 (.D(temp_data[1]), .SP(clock_enable_21), 
            .CK(clock), .Q(temperature_data[1]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(431[8] 440[4])
    defparam temperature_data__i2.GSR = "DISABLED";
    FD1P3AX sec_u_i0_i5 (.D(uart_data_R[5]), .SP(sys_clk_N_7_enable_33), 
            .CK(sys_clk_N_7), .Q(sec_u[5]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam sec_u_i0_i5.GSR = "DISABLED";
    FD1P3AX sec_u_i0_i4 (.D(uart_data_R[4]), .SP(sys_clk_N_7_enable_33), 
            .CK(sys_clk_N_7), .Q(sec_u[4]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam sec_u_i0_i4.GSR = "DISABLED";
    FD1P3AX sec_u_i0_i3 (.D(uart_data_R[3]), .SP(sys_clk_N_7_enable_33), 
            .CK(sys_clk_N_7), .Q(sec_u[3]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam sec_u_i0_i3.GSR = "DISABLED";
    FD1P3AX sec_u_i0_i2 (.D(uart_data_R[2]), .SP(sys_clk_N_7_enable_33), 
            .CK(sys_clk_N_7), .Q(sec_u[2]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam sec_u_i0_i2.GSR = "DISABLED";
    FD1P3AX sec_u_i0_i1 (.D(uart_data_R[1]), .SP(sys_clk_N_7_enable_33), 
            .CK(sys_clk_N_7), .Q(sec_u[1]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam sec_u_i0_i1.GSR = "DISABLED";
    FD1P3AX min_h_u_i0_i3 (.D(uart_data_R[7]), .SP(sys_clk_N_7_enable_39), 
            .CK(sys_clk_N_7), .Q(min_h_u[3]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam min_h_u_i0_i3.GSR = "DISABLED";
    FD1P3AX min_h_u_i0_i2 (.D(uart_data_R[6]), .SP(sys_clk_N_7_enable_39), 
            .CK(sys_clk_N_7), .Q(min_h_u[2]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam min_h_u_i0_i2.GSR = "DISABLED";
    FD1P3AX min_h_u_i0_i1 (.D(uart_data_R[5]), .SP(sys_clk_N_7_enable_39), 
            .CK(sys_clk_N_7), .Q(min_h_u[1]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam min_h_u_i0_i1.GSR = "DISABLED";
    FD1P3AX min_l_u_i0_i3 (.D(uart_data_R[3]), .SP(sys_clk_N_7_enable_39), 
            .CK(sys_clk_N_7), .Q(min_l_u[3]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam min_l_u_i0_i3.GSR = "DISABLED";
    FD1P3AX min_l_u_i0_i2 (.D(uart_data_R[2]), .SP(sys_clk_N_7_enable_39), 
            .CK(sys_clk_N_7), .Q(min_l_u[2]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam min_l_u_i0_i2.GSR = "DISABLED";
    FD1P3AX min_l_u_i0_i1 (.D(uart_data_R[1]), .SP(sys_clk_N_7_enable_39), 
            .CK(sys_clk_N_7), .Q(min_l_u[1]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam min_l_u_i0_i1.GSR = "DISABLED";
    FD1P3AX hour_h_u_i0_i3 (.D(uart_data_R[7]), .SP(sys_clk_N_7_enable_45), 
            .CK(sys_clk_N_7), .Q(hour_h_u[3]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam hour_h_u_i0_i3.GSR = "DISABLED";
    FD1P3AX hour_h_u_i0_i2 (.D(uart_data_R[6]), .SP(sys_clk_N_7_enable_45), 
            .CK(sys_clk_N_7), .Q(hour_h_u[2]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam hour_h_u_i0_i2.GSR = "DISABLED";
    FD1P3AX hour_h_u_i0_i1 (.D(uart_data_R[5]), .SP(sys_clk_N_7_enable_45), 
            .CK(sys_clk_N_7), .Q(hour_h_u[1]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam hour_h_u_i0_i1.GSR = "DISABLED";
    FD1P3AX hour_l_u_i0_i3 (.D(uart_data_R[3]), .SP(sys_clk_N_7_enable_45), 
            .CK(sys_clk_N_7), .Q(hour_l_u[3]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam hour_l_u_i0_i3.GSR = "DISABLED";
    FD1P3AX hour_l_u_i0_i2 (.D(uart_data_R[2]), .SP(sys_clk_N_7_enable_45), 
            .CK(sys_clk_N_7), .Q(hour_l_u[2]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam hour_l_u_i0_i2.GSR = "DISABLED";
    FD1P3AX hour_l_u_i0_i1 (.D(uart_data_R[1]), .SP(sys_clk_N_7_enable_45), 
            .CK(sys_clk_N_7), .Q(hour_l_u[1]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam hour_l_u_i0_i1.GSR = "DISABLED";
    FD1P3AX temp_p_i0_i3 (.D(uart_data_R[3]), .SP(sys_clk_N_7_enable_48), 
            .CK(sys_clk_N_7), .Q(temp_p[3]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam temp_p_i0_i3.GSR = "ENABLED";
    FD1P3AX temp_p_i0_i2 (.D(uart_data_R[2]), .SP(sys_clk_N_7_enable_48), 
            .CK(sys_clk_N_7), .Q(temp_p[2]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam temp_p_i0_i2.GSR = "ENABLED";
    FD1P3AX temp_p_i0_i1 (.D(uart_data_R[1]), .SP(sys_clk_N_7_enable_48), 
            .CK(sys_clk_N_7), .Q(temp_p[1]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam temp_p_i0_i1.GSR = "ENABLED";
    FD1P3AX temp_l_i0_i3 (.D(uart_data_R[3]), .SP(sys_clk_N_7_enable_50), 
            .CK(sys_clk_N_7), .Q(temp_l[3]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam temp_l_i0_i3.GSR = "ENABLED";
    FD1P3AX temp_l_i0_i2 (.D(uart_data_R[2]), .SP(sys_clk_N_7_enable_50), 
            .CK(sys_clk_N_7), .Q(temp_l[2]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam temp_l_i0_i2.GSR = "ENABLED";
    FD1P3AX min_l_2263__i1 (.D(n30), .SP(clock_enable_24), .CK(clock), 
            .Q(min_l[1]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(101[22:33])
    defparam min_l_2263__i1.GSR = "ENABLED";
    IB key_bus_pad_1 (.I(key_bus[1]), .O(key_bus_c_1));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(25[19:26])
    IB key_bus_pad_0 (.I(key_bus[0]), .O(key_bus_c_0));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(25[19:26])
    FD1P3AX min_l_2263__i2 (.D(n29731), .SP(clock_enable_24), .CK(clock), 
            .Q(min_l[2]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(101[22:33])
    defparam min_l_2263__i2.GSR = "ENABLED";
    FD1P3AX min_l_2263__i3 (.D(n28_adj_1831), .SP(clock_enable_24), .CK(clock), 
            .Q(min_l[3]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(101[22:33])
    defparam min_l_2263__i3.GSR = "ENABLED";
    FD1P3AX hour_l_2264__i1 (.D(n26523), .SP(clock_enable_27), .CK(clock), 
            .Q(hour_l[1]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(112[22:35])
    defparam hour_l_2264__i1.GSR = "ENABLED";
    FD1P3AX hour_l_2264__i2 (.D(n26525), .SP(clock_enable_27), .CK(clock), 
            .Q(hour_l[2]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(112[22:35])
    defparam hour_l_2264__i2.GSR = "ENABLED";
    FD1P3AX hour_l_2264__i3 (.D(n28), .SP(clock_enable_27), .CK(clock), 
            .Q(hour_l[3]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(112[22:35])
    defparam hour_l_2264__i3.GSR = "ENABLED";
    FD1S3AX uart_cnt_2265__i1 (.D(n84), .CK(clk_1us), .Q(uart_cnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265__i1.GSR = "DISABLED";
    FD1S3AX uart_cnt_2265__i2 (.D(n83), .CK(clk_1us), .Q(uart_cnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265__i2.GSR = "DISABLED";
    FD1S3AX uart_cnt_2265__i3 (.D(n82), .CK(clk_1us), .Q(uart_cnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265__i3.GSR = "DISABLED";
    FD1S3AX uart_cnt_2265__i4 (.D(n81), .CK(clk_1us), .Q(uart_cnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265__i4.GSR = "DISABLED";
    FD1S3AX uart_cnt_2265__i5 (.D(n80), .CK(clk_1us), .Q(uart_cnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265__i5.GSR = "DISABLED";
    FD1S3AX uart_cnt_2265__i6 (.D(n79), .CK(clk_1us), .Q(uart_cnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265__i6.GSR = "DISABLED";
    FD1S3AX uart_cnt_2265__i7 (.D(n78), .CK(clk_1us), .Q(uart_cnt[7])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265__i7.GSR = "DISABLED";
    FD1S3AX uart_cnt_2265__i8 (.D(n77), .CK(clk_1us), .Q(uart_cnt[8])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265__i8.GSR = "DISABLED";
    FD1S3AX uart_cnt_2265__i9 (.D(n76), .CK(clk_1us), .Q(uart_cnt[9])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265__i9.GSR = "DISABLED";
    FD1S3AX uart_cnt_2265__i10 (.D(n75), .CK(clk_1us), .Q(uart_cnt[10])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265__i10.GSR = "DISABLED";
    FD1S3AX uart_cnt_2265__i11 (.D(n74), .CK(clk_1us), .Q(uart_cnt[11])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265__i11.GSR = "DISABLED";
    FD1S3AX uart_cnt_2265__i12 (.D(n73_adj_1826), .CK(clk_1us), .Q(uart_cnt[12])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265__i12.GSR = "DISABLED";
    FD1S3AX uart_cnt_2265__i13 (.D(n72_adj_1825), .CK(clk_1us), .Q(uart_cnt[13])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265__i13.GSR = "DISABLED";
    FD1S3AX uart_cnt_2265__i14 (.D(n71_adj_1824), .CK(clk_1us), .Q(uart_cnt[14])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265__i14.GSR = "DISABLED";
    FD1S3AX uart_cnt_2265__i15 (.D(n70_adj_1823), .CK(clk_1us), .Q(uart_cnt[15])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265__i15.GSR = "DISABLED";
    FD1P3AX min_h_i0_i1 (.D(n172), .SP(clock_enable_33), .CK(clock), .Q(min_h[1]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(82[10] 124[8])
    defparam min_h_i0_i1.GSR = "ENABLED";
    FD1P3AX min_h_i0_i2 (.D(n171), .SP(clock_enable_33), .CK(clock), .Q(min_h[2]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(82[10] 124[8])
    defparam min_h_i0_i2.GSR = "ENABLED";
    FD1P3AX min_h_i0_i3 (.D(n170), .SP(clock_enable_33), .CK(clock), .Q(min_h[3]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(82[10] 124[8])
    defparam min_h_i0_i3.GSR = "ENABLED";
    FD1P3AX Beep_status_uart_i0_i1 (.D(uart_data_R[1]), .SP(sys_clk_N_7_enable_54), 
            .CK(sys_clk_N_7), .Q(Beep_status_uart[1]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam Beep_status_uart_i0_i1.GSR = "DISABLED";
    LUT4 i5_3_lut_rep_333_4_lut (.A(usart_recieve_state[3]), .B(n29710), 
         .C(n10), .D(usart_recieve_state[4]), .Z(n29609)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i5_3_lut_rep_333_4_lut.init = 16'hfffe;
    LUT4 i15065_3_lut_rep_296 (.A(n15254), .B(n15687), .C(n29676), .Z(n29572)) /* synthesis lut_function=(A (B)+!A (B (C))) */ ;
    defparam i15065_3_lut_rep_296.init = 16'hc8c8;
    FD1P3AX Beep_status_uart_i0_i2 (.D(uart_data_R[2]), .SP(sys_clk_N_7_enable_54), 
            .CK(sys_clk_N_7), .Q(Beep_status_uart[2]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam Beep_status_uart_i0_i2.GSR = "DISABLED";
    FD1P3AX Beep_status_uart_i0_i3 (.D(uart_data_R[3]), .SP(sys_clk_N_7_enable_54), 
            .CK(sys_clk_N_7), .Q(Beep_status_uart[3]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam Beep_status_uart_i0_i3.GSR = "DISABLED";
    FD1P3AX Beep_status_uart_i0_i4 (.D(uart_data_R[4]), .SP(sys_clk_N_7_enable_54), 
            .CK(sys_clk_N_7), .Q(Beep_status_uart[4]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam Beep_status_uart_i0_i4.GSR = "DISABLED";
    FD1P3AX usart_send_state_FSM__i2 (.D(n2426), .SP(clk_1us_enable_11), 
            .CK(clk_1us), .Q(usart_send_state[0]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(269[9] 322[16])
    defparam usart_send_state_FSM__i2.GSR = "ENABLED";
    FD1P3AY usart_send_state_FSM__i3 (.D(usart_send_state[0]), .SP(clk_1us_enable_11), 
            .CK(clk_1us), .Q(usart_send_state_31__N_277));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(269[9] 322[16])
    defparam usart_send_state_FSM__i3.GSR = "ENABLED";
    PFUMX i22295 (.BLUT(n28608), .ALUT(n28607), .C0(cnt_adj_1865[0]), 
          .Z(n28609));
    LUT4 i3_3_lut_4_lut (.A(n15254), .B(n15687), .C(n29676), .D(time_set_flag), 
         .Z(n8_adj_1846)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;
    defparam i3_3_lut_4_lut.init = 16'h0008;
    FD1P3AX hour_h_i0_i1 (.D(n162), .SP(clock_enable_33), .CK(clock), 
            .Q(hour_h[1]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(82[10] 124[8])
    defparam hour_h_i0_i1.GSR = "ENABLED";
    LUT4 i1_2_lut_3_lut_4_lut_adj_359 (.A(usart_recieve_state[4]), .B(n29595), 
         .C(n295), .D(n27779), .Z(n27598)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i1_2_lut_3_lut_4_lut_adj_359.init = 16'h0080;
    FD1P3AX hour_h_i0_i2 (.D(n161), .SP(clock_enable_33), .CK(clock), 
            .Q(hour_h[2]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(82[10] 124[8])
    defparam hour_h_i0_i2.GSR = "ENABLED";
    FD1P3AX hour_h_i0_i3 (.D(n160), .SP(clock_enable_33), .CK(clock), 
            .Q(hour_h[3]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(82[10] 124[8])
    defparam hour_h_i0_i3.GSR = "ENABLED";
    LUT4 i1_2_lut_3_lut_4_lut_adj_360 (.A(usart_recieve_state[4]), .B(n29595), 
         .C(n294), .D(n27779), .Z(n27597)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i1_2_lut_3_lut_4_lut_adj_360.init = 16'h0080;
    LUT4 cnt_4__bdd_4_lut_22369 (.A(cnt_adj_1865[4]), .B(cnt_adj_1865[2]), 
         .C(cnt_adj_1865[3]), .D(cnt_adj_1865[1]), .Z(n28608)) /* synthesis lut_function=(!(A (B (C)+!B (C (D)))+!A !(B+!(D)))) */ ;
    defparam cnt_4__bdd_4_lut_22369.init = 16'h4e7f;
    LUT4 i1_2_lut_4_lut (.A(n17), .B(usart_recieve_cnt[1]), .C(n29631), 
         .D(usart_recieve_cnt[0]), .Z(sys_clk_N_7_enable_45)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(140[10] 143[8])
    defparam i1_2_lut_4_lut.init = 16'h0002;
    LUT4 i1_2_lut_4_lut_adj_361 (.A(n17), .B(usart_recieve_cnt[1]), .C(n29631), 
         .D(usart_recieve_cnt[0]), .Z(sys_clk_N_7_enable_39)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(140[10] 143[8])
    defparam i1_2_lut_4_lut_adj_361.init = 16'h0200;
    LUT4 i1_2_lut_3_lut_adj_362 (.A(n75_adj_1835), .B(usart_recieve_cnt[1]), 
         .C(usart_recieve_cnt[0]), .Z(sys_clk_N_7_enable_15)) /* synthesis lut_function=(!((B+(C))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i1_2_lut_3_lut_adj_362.init = 16'h0202;
    LUT4 i18925_2_lut_rep_378 (.A(hour_l[1]), .B(hour_l[0]), .Z(n29654)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(112[22:35])
    defparam i18925_2_lut_rep_378.init = 16'h8888;
    LUT4 i63_2_lut_rep_338_3_lut (.A(hour_l[1]), .B(hour_l[0]), .C(hour_l[2]), 
         .Z(n29614)) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(112[22:35])
    defparam i63_2_lut_rep_338_3_lut.init = 16'h7878;
    LUT4 i18936_3_lut_4_lut (.A(hour_l[1]), .B(hour_l[0]), .C(hour_l[2]), 
         .D(hour_l[3]), .Z(n22_adj_1827)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(112[22:35])
    defparam i18936_3_lut_4_lut.init = 16'h7f80;
    LUT4 i63_2_lut_rep_379 (.A(hour_l[0]), .B(hour_l[1]), .Z(n29655)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(112[22:35])
    defparam i63_2_lut_rep_379.init = 16'h6666;
    LUT4 i1_3_lut_4_lut_adj_363 (.A(hour_l[0]), .B(hour_l[1]), .C(n27414), 
         .D(clock_flag_N_372), .Z(n27415)) /* synthesis lut_function=(!(A (B+!(C (D)))+!A !(B (C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(112[22:35])
    defparam i1_3_lut_4_lut_adj_363.init = 16'h6000;
    LUT4 i15268_3_lut_rep_281 (.A(n29572), .B(key_bus_c_0), .C(time_set_flag), 
         .Z(n29557)) /* synthesis lut_function=(A (B)+!A (B (C))) */ ;
    defparam i15268_3_lut_rep_281.init = 16'hc8c8;
    LUT4 i1_2_lut_rep_272_3_lut_4_lut (.A(usart_recieve_state[4]), .B(n29595), 
         .C(n3), .D(n27779), .Z(n29548)) /* synthesis lut_function=(A (B (C+!(D))+!B (C))+!A (C)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i1_2_lut_rep_272_3_lut_4_lut.init = 16'hf0f8;
    LUT4 i1_2_lut_3_lut_adj_364 (.A(n75_adj_1835), .B(usart_recieve_cnt[1]), 
         .C(usart_recieve_cnt[0]), .Z(sys_clk_N_7_enable_50)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i1_2_lut_3_lut_adj_364.init = 16'h2020;
    LUT4 i1_2_lut_rep_380 (.A(usart_recieve_state[4]), .B(usart_recieve_state[5]), 
         .Z(n29656)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i1_2_lut_rep_380.init = 16'hbbbb;
    LUT4 i1_3_lut_4_lut_adj_365 (.A(usart_recieve_state[4]), .B(usart_recieve_state[5]), 
         .C(n24), .D(usart_recieve_state[1]), .Z(n13)) /* synthesis lut_function=(A (C+(D))+!A (B (C)+!B (C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i1_3_lut_4_lut_adj_365.init = 16'hfbf0;
    LUT4 i14443_2_lut (.A(hour_l_u[3]), .B(time_set_flag), .Z(n165)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(96[10] 124[8])
    defparam i14443_2_lut.init = 16'h8888;
    LUT4 i1_2_lut_rep_358_3_lut (.A(usart_recieve_state[4]), .B(usart_recieve_state[5]), 
         .C(n26), .Z(n29634)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i1_2_lut_rep_358_3_lut.init = 16'h4040;
    CCU2D usart_send_cnt_2266_add_4_27 (.A0(usart_send_cnt[25]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(usart_send_cnt[26]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n25052), .COUT(n25053), .S0(n140), 
          .S1(n139));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266_add_4_27.INIT0 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_27.INIT1 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_27.INJECT1_0 = "NO";
    defparam usart_send_cnt_2266_add_4_27.INJECT1_1 = "NO";
    CCU2D usart_send_cnt_2266_add_4_25 (.A0(usart_send_cnt[23]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(usart_send_cnt[24]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n25051), .COUT(n25052), .S0(n142), 
          .S1(n141));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266_add_4_25.INIT0 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_25.INIT1 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_25.INJECT1_0 = "NO";
    defparam usart_send_cnt_2266_add_4_25.INJECT1_1 = "NO";
    CCU2D usart_send_cnt_2266_add_4_23 (.A0(usart_send_cnt[21]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(usart_send_cnt[22]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n25050), .COUT(n25051), .S0(n144), 
          .S1(n143));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266_add_4_23.INIT0 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_23.INIT1 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_23.INJECT1_0 = "NO";
    defparam usart_send_cnt_2266_add_4_23.INJECT1_1 = "NO";
    LUT4 i2_3_lut (.A(n27644), .B(n290), .C(usart_recieve_cnt[4]), .Z(n27645)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;
    defparam i2_3_lut.init = 16'h0808;
    CCU2D uart_cnt_2265_add_4_3 (.A0(uart_cnt[1]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(uart_cnt[2]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24960), .COUT(n24961), .S0(n84), .S1(n83));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265_add_4_3.INIT0 = 16'hfaaa;
    defparam uart_cnt_2265_add_4_3.INIT1 = 16'hfaaa;
    defparam uart_cnt_2265_add_4_3.INJECT1_0 = "NO";
    defparam uart_cnt_2265_add_4_3.INJECT1_1 = "NO";
    CCU2D usart_send_cnt_2266_add_4_21 (.A0(usart_send_cnt[19]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(usart_send_cnt[20]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n25049), .COUT(n25050), .S0(n146), 
          .S1(n145));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266_add_4_21.INIT0 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_21.INIT1 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_21.INJECT1_0 = "NO";
    defparam usart_send_cnt_2266_add_4_21.INJECT1_1 = "NO";
    CCU2D uart_cnt_2265_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(uart_cnt[0]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .COUT(n24960), .S1(n85));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265_add_4_1.INIT0 = 16'hF000;
    defparam uart_cnt_2265_add_4_1.INIT1 = 16'h0555;
    defparam uart_cnt_2265_add_4_1.INJECT1_0 = "NO";
    defparam uart_cnt_2265_add_4_1.INJECT1_1 = "NO";
    LUT4 i1_2_lut_rep_297_4_lut (.A(n29627), .B(n29675), .C(usart_recieve_state[0]), 
         .D(usart_recieve_state[4]), .Z(n29573)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i1_2_lut_rep_297_4_lut.init = 16'h0200;
    LUT4 i19_4_lut_adj_366 (.A(uart_data_R[3]), .B(usart_recieve_state[3]), 
         .C(n29609), .D(n29548), .Z(n26877)) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(201[18] 239[16])
    defparam i19_4_lut_adj_366.init = 16'hca0a;
    LUT4 i21_4_lut (.A(uart_data_R[4]), .B(usart_recieve_state[4]), .C(n29609), 
         .D(n8), .Z(n26871)) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(201[18] 239[16])
    defparam i21_4_lut.init = 16'hca0a;
    LUT4 i1_3_lut_adj_367 (.A(n3), .B(n29595), .C(n27779), .Z(n8)) /* synthesis lut_function=(A+!((C)+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(201[18] 239[16])
    defparam i1_3_lut_adj_367.init = 16'haeae;
    CCU2D usart_send_cnt_2266_add_4_19 (.A0(usart_send_cnt[17]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(usart_send_cnt[18]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n25048), .COUT(n25049), .S0(n148), 
          .S1(n147));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266_add_4_19.INIT0 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_19.INIT1 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_19.INJECT1_0 = "NO";
    defparam usart_send_cnt_2266_add_4_19.INJECT1_1 = "NO";
    LUT4 i1_2_lut_rep_430 (.A(uart_en_R_1), .B(uart_en_R_0), .Z(sys_clk_N_7_enable_57)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(13[19:28])
    defparam i1_2_lut_rep_430.init = 16'h4444;
    LUT4 i1_2_lut_rep_334_3_lut (.A(uart_en_R_1), .B(uart_en_R_0), .C(n18_adj_1819), 
         .Z(n29610)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(13[19:28])
    defparam i1_2_lut_rep_334_3_lut.init = 16'h4040;
    LUT4 i1_2_lut_3_lut_adj_368 (.A(uart_en_R_1), .B(uart_en_R_0), .C(n18_adj_1819), 
         .Z(n18822)) /* synthesis lut_function=(!(A+((C)+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(13[19:28])
    defparam i1_2_lut_3_lut_adj_368.init = 16'h0404;
    LUT4 cnt_4__bdd_2_lut_22368 (.A(cnt_adj_1865[4]), .B(cnt_adj_1865[2]), 
         .Z(n28607)) /* synthesis lut_function=(!(A+!(B))) */ ;
    defparam cnt_4__bdd_2_lut_22368.init = 16'h4444;
    LUT4 i18907_3_lut_4_lut (.A(min_l[1]), .B(min_l[0]), .C(min_l[2]), 
         .D(min_l[3]), .Z(n22_adj_1829)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(101[22:33])
    defparam i18907_3_lut_4_lut.init = 16'h7f80;
    CCU2D usart_send_cnt_2266_add_4_17 (.A0(usart_send_cnt[15]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(usart_send_cnt[16]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n25047), .COUT(n25048), .S0(n150), 
          .S1(n149));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266_add_4_17.INIT0 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_17.INIT1 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_17.INJECT1_0 = "NO";
    defparam usart_send_cnt_2266_add_4_17.INJECT1_1 = "NO";
    LUT4 i22168_4_lut (.A(n29575), .B(rx_flag), .C(n31), .D(n29636), 
         .Z(sys_clk_c_enable_47)) /* synthesis lut_function=(!(A (B (C))+!A (B (C+!(D))))) */ ;
    defparam i22168_4_lut.init = 16'h3f3b;
    LUT4 i1_2_lut_rep_434 (.A(usart_recieve_state[0]), .B(usart_recieve_state[7]), 
         .Z(n29710)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i1_2_lut_rep_434.init = 16'heeee;
    LUT4 i1_2_lut_rep_373_3_lut (.A(usart_recieve_state[0]), .B(usart_recieve_state[7]), 
         .C(usart_recieve_state[3]), .Z(n29649)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i1_2_lut_rep_373_3_lut.init = 16'hfefe;
    LUT4 i2_2_lut_3_lut_4_lut (.A(usart_recieve_state[0]), .B(usart_recieve_state[7]), 
         .C(usart_recieve_state[3]), .D(usart_recieve_state[2]), .Z(n7_adj_1844)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i2_2_lut_3_lut_4_lut.init = 16'hfeff;
    CCU2D usart_send_cnt_2266_add_4_15 (.A0(usart_send_cnt[13]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(usart_send_cnt[14]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n25046), .COUT(n25047), .S0(n152), 
          .S1(n151));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266_add_4_15.INIT0 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_15.INIT1 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_15.INJECT1_0 = "NO";
    defparam usart_send_cnt_2266_add_4_15.INJECT1_1 = "NO";
    CCU2D usart_send_cnt_2266_add_4_13 (.A0(usart_send_cnt[11]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(usart_send_cnt[12]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n25045), .COUT(n25046), .S0(n154), 
          .S1(n153));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266_add_4_13.INIT0 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_13.INIT1 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_13.INJECT1_0 = "NO";
    defparam usart_send_cnt_2266_add_4_13.INJECT1_1 = "NO";
    LUT4 i2_2_lut_3_lut_4_lut_adj_369 (.A(n29688), .B(n29634), .C(clock_flag_N_372), 
         .D(usart_recieve_state[1]), .Z(n7921)) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (C)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i2_2_lut_3_lut_4_lut_adj_369.init = 16'hf8f0;
    LUT4 i1_2_lut_3_lut_4_lut_adj_370 (.A(n29688), .B(n29634), .C(n15254), 
         .D(usart_recieve_state[1]), .Z(n7918)) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (C)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i1_2_lut_3_lut_4_lut_adj_370.init = 16'hf8f0;
    LUT4 i2_3_lut_adj_371 (.A(usart_recieve_state[2]), .B(usart_recieve_state[0]), 
         .C(usart_recieve_state[3]), .Z(n26)) /* synthesis lut_function=(!((B+(C))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i2_3_lut_adj_371.init = 16'h0202;
    FD1P3IX usart_recieve_state_i0_i3 (.D(n26877), .SP(sys_clk_N_7_enable_57), 
            .CD(n18822), .CK(sys_clk_N_7), .Q(usart_recieve_state[3]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam usart_recieve_state_i0_i3.GSR = "ENABLED";
    FD1P3IX usart_recieve_state_i0_i4 (.D(n26871), .SP(sys_clk_N_7_enable_57), 
            .CD(n18822), .CK(sys_clk_N_7), .Q(usart_recieve_state[4]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam usart_recieve_state_i0_i4.GSR = "ENABLED";
    FD1P3IX usart_recieve_state_i0_i7 (.D(n26855), .SP(sys_clk_N_7_enable_57), 
            .CD(n18822), .CK(sys_clk_N_7), .Q(usart_recieve_state[7]));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam usart_recieve_state_i0_i7.GSR = "ENABLED";
    LUT4 i21701_2_lut_4_lut (.A(n29572), .B(key_bus_c_0), .C(time_set_flag), 
         .D(key_bus_c_1), .Z(clock_enable_24)) /* synthesis lut_function=(A (B+!(D))+!A (B (C+!(D))+!B !(D))) */ ;
    defparam i21701_2_lut_4_lut.init = 16'hc8ff;
    LUT4 i1_2_lut_3_lut_4_lut_adj_372 (.A(uart_data_R[0]), .B(n29640), .C(n29634), 
         .D(n29688), .Z(n27576)) /* synthesis lut_function=(A (B (C (D)))+!A (C (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(224[28:46])
    defparam i1_2_lut_3_lut_4_lut_adj_372.init = 16'hd000;
    CCU2D usart_send_cnt_2266_add_4_11 (.A0(usart_send_cnt[9]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(usart_send_cnt[10]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n25044), .COUT(n25045), .S0(n156), 
          .S1(n155));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266_add_4_11.INIT0 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_11.INIT1 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_11.INJECT1_0 = "NO";
    defparam usart_send_cnt_2266_add_4_11.INJECT1_1 = "NO";
    LUT4 select_939_Select_0_i3_4_lut (.A(n4921), .B(n29668), .C(n27541), 
         .D(uart_data_w[0]), .Z(uart_data_w_7__N_345[0])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(269[9] 322[16])
    defparam select_939_Select_0_i3_4_lut.init = 16'heca0;
    LUT4 mux_1388_i1_4_lut (.A(uart_data_w[0]), .B(n4901), .C(n16625), 
         .D(usart_send_cnt[2]), .Z(n4921)) /* synthesis lut_function=(A (B+(C+(D)))+!A !(B (C)+!B (C+!(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(290[21] 297[28])
    defparam mux_1388_i1_4_lut.init = 16'hafac;
    LUT4 i14566_4_lut (.A(temperature_data[8]), .B(usart_send_cnt[1]), .C(temperature_data[0]), 
         .D(usart_send_cnt[0]), .Z(n4901)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(290[21] 297[28])
    defparam i14566_4_lut.init = 16'hc088;
    FD1S3IX i76_255 (.D(n29672), .CK(clock), .CD(n2733), .Q(time_set_ready_flag));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(82[10] 124[8])
    defparam i76_255.GSR = "ENABLED";
    CCU2D usart_send_cnt_2266_add_4_9 (.A0(usart_send_cnt[7]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(usart_send_cnt[8]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n25043), .COUT(n25044), .S0(n158), 
          .S1(n157));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266_add_4_9.INIT0 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_9.INIT1 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_9.INJECT1_0 = "NO";
    defparam usart_send_cnt_2266_add_4_9.INJECT1_1 = "NO";
    LUT4 i2_3_lut_adj_373 (.A(usart_recieve_cnt[5]), .B(usart_recieve_cnt[7]), 
         .C(usart_recieve_cnt[6]), .Z(n21236)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i2_3_lut_adj_373.init = 16'hfefe;
    CCU2D usart_send_cnt_2266_add_4_7 (.A0(usart_send_cnt[5]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(usart_send_cnt[6]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n25042), .COUT(n25043), .S0(n160_adj_1810), 
          .S1(n159));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266_add_4_7.INIT0 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_7.INIT1 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_7.INJECT1_0 = "NO";
    defparam usart_send_cnt_2266_add_4_7.INJECT1_1 = "NO";
    LUT4 i2688_3_lut_4_lut (.A(sec[3]), .B(n29641), .C(sec[4]), .D(sec[5]), 
         .Z(n42)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(97[16:24])
    defparam i2688_3_lut_4_lut.init = 16'h7f80;
    LUT4 mux_121_i6_3_lut_4_lut (.A(uart_data_R[0]), .B(n29640), .C(n290), 
         .D(usart_recieve_cnt[5]), .Z(n456)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(191[16:34])
    defparam mux_121_i6_3_lut_4_lut.init = 16'hf1e0;
    LUT4 min_l_2263_mux_6_i1_4_lut (.A(min_l_u[0]), .B(min_l[0]), .C(n2749), 
         .D(time_set_flag), .Z(n31_adj_1832)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+(D)))+!A (B+!(C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(101[22:33])
    defparam min_l_2263_mux_6_i1_4_lut.init = 16'h3a30;
    LUT4 i769_4_lut (.A(n15254), .B(key_bus_c_1), .C(n8_adj_1846), .D(n29557), 
         .Z(n2749)) /* synthesis lut_function=(A ((C (D))+!B)+!A !(B)) */ ;
    defparam i769_4_lut.init = 16'hb333;
    LUT4 mux_53_i3_4_lut (.A(n45), .B(sec_u[2]), .C(time_set_flag), .D(n7918), 
         .Z(n183)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(96[10] 124[8])
    defparam mux_53_i3_4_lut.init = 16'hc0ca;
    LUT4 mux_53_i2_4_lut (.A(n46), .B(sec_u[1]), .C(time_set_flag), .D(n7918), 
         .Z(n184)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(96[10] 124[8])
    defparam mux_53_i2_4_lut.init = 16'hc0ca;
    CCU2D usart_send_cnt_2266_add_4_5 (.A0(usart_send_cnt[3]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(usart_send_cnt[4]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n25041), .COUT(n25042), .S0(n162_adj_1811), 
          .S1(n161_adj_1809));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266_add_4_5.INIT0 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_5.INIT1 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_5.INJECT1_0 = "NO";
    defparam usart_send_cnt_2266_add_4_5.INJECT1_1 = "NO";
    LUT4 i1_2_lut_4_lut_adj_374 (.A(usart_recieve_state[4]), .B(n10), .C(n29649), 
         .D(n29610), .Z(sys_clk_N_7_enable_23)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i1_2_lut_4_lut_adj_374.init = 16'hfe00;
    LUT4 i22181_4_lut (.A(clock_flag_N_372), .B(time_set_flag), .C(n29672), 
         .D(n29571), .Z(clock_flag_N_368)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(85[10] 124[8])
    defparam i22181_4_lut.init = 16'h0020;
    LUT4 mux_51_i4_4_lut (.A(n70), .B(min_h_u[3]), .C(time_set_flag), 
         .D(n7921), .Z(n170)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(96[10] 124[8])
    defparam mux_51_i4_4_lut.init = 16'hc0ca;
    LUT4 i2_3_lut_4_lut_adj_375 (.A(n18_adj_1819), .B(sys_clk_N_7_enable_57), 
         .C(n27404), .D(n29660), .Z(n17)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(140[10] 143[8])
    defparam i2_3_lut_4_lut_adj_375.init = 16'h8000;
    CCU2D add_88_7 (.A0(usart_recieve_cnt[5]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(usart_recieve_cnt[6]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24936), .COUT(n24937), .S0(n290), .S1(n289));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(207[82:104])
    defparam add_88_7.INIT0 = 16'h5aaa;
    defparam add_88_7.INIT1 = 16'h5aaa;
    defparam add_88_7.INJECT1_0 = "NO";
    defparam add_88_7.INJECT1_1 = "NO";
    LUT4 i21756_3_lut (.A(min_h[3]), .B(min_h[2]), .C(min_h[1]), .Z(clock_flag_N_372)) /* synthesis lut_function=(A+(B (C))) */ ;
    defparam i21756_3_lut.init = 16'heaea;
    LUT4 i1_2_lut_3_lut_4_lut_adj_376 (.A(n29573), .B(n27779), .C(usart_recieve_state[6]), 
         .D(n3), .Z(n7_adj_1808)) /* synthesis lut_function=(A (B (C (D))+!B (C))+!A (C (D))) */ ;
    defparam i1_2_lut_3_lut_4_lut_adj_376.init = 16'hf020;
    CCU2D usart_send_cnt_2266_add_4_3 (.A0(usart_send_cnt[1]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(usart_send_cnt[2]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n25040), .COUT(n25041), .S0(n164), 
          .S1(n163_adj_1818));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266_add_4_3.INIT0 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_3.INIT1 = 16'hfaaa;
    defparam usart_send_cnt_2266_add_4_3.INJECT1_0 = "NO";
    defparam usart_send_cnt_2266_add_4_3.INJECT1_1 = "NO";
    CCU2D usart_send_cnt_2266_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(usart_send_cnt[0]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .COUT(n25040), .S1(n165_adj_1814));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266_add_4_1.INIT0 = 16'hF000;
    defparam usart_send_cnt_2266_add_4_1.INIT1 = 16'h0555;
    defparam usart_send_cnt_2266_add_4_1.INJECT1_0 = "NO";
    defparam usart_send_cnt_2266_add_4_1.INJECT1_1 = "NO";
    LUT4 mux_51_i1_4_lut (.A(n73), .B(min_h_u[0]), .C(time_set_flag), 
         .D(n7921), .Z(n173)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(96[10] 124[8])
    defparam mux_51_i1_4_lut.init = 16'hc0ca;
    LUT4 i3_4_lut_adj_377 (.A(sys_clk_N_7_enable_57), .B(usart_recieve_state[1]), 
         .C(n27453), .D(n4_adj_1840), .Z(sys_clk_N_7_enable_54)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(13[19:28])
    defparam i3_4_lut_adj_377.init = 16'h8000;
    LUT4 i1_3_lut_adj_378 (.A(n8_adj_1834), .B(usart_recieve_state[4]), 
         .C(n15384), .Z(n4_adj_1840)) /* synthesis lut_function=(!(A (B)+!A (B+!(C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(13[19:28])
    defparam i1_3_lut_adj_378.init = 16'h3232;
    LUT4 i1_2_lut_3_lut_4_lut_adj_379 (.A(n29573), .B(n27779), .C(usart_recieve_state[5]), 
         .D(n3), .Z(n7_adj_1806)) /* synthesis lut_function=(A (B (C (D))+!B (C))+!A (C (D))) */ ;
    defparam i1_2_lut_3_lut_4_lut_adj_379.init = 16'hf020;
    LUT4 i2709_2_lut_3_lut_4_lut (.A(min_h[0]), .B(n29676), .C(min_h[2]), 
         .D(min_h[1]), .Z(n71)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(106[21:33])
    defparam i2709_2_lut_3_lut_4_lut.init = 16'h78f0;
    FD1P3IX usart_send_cnt_2266__i31 (.D(n134), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[31])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i31.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i30 (.D(n135), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[30])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i30.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i29 (.D(n136), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[29])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i29.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i28 (.D(n137), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[28])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i28.GSR = "ENABLED";
    LUT4 i2702_2_lut_3_lut (.A(min_h[0]), .B(n29676), .C(min_h[1]), .Z(n72)) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(106[21:33])
    defparam i2702_2_lut_3_lut.init = 16'h7878;
    FD1P3IX usart_send_cnt_2266__i27 (.D(n138), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[27])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i27.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i26 (.D(n139), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[26])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i26.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i25 (.D(n140), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[25])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i25.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i24 (.D(n141), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[24])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i24.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i23 (.D(n142), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[23])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i23.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i22 (.D(n143), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[22])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i22.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i21 (.D(n144), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[21])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i21.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i20 (.D(n145), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[20])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i20.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i19 (.D(n146), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[19])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i19.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i18 (.D(n147), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[18])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i18.GSR = "ENABLED";
    LUT4 i1_3_lut_4_lut_adj_380 (.A(n29654), .B(hour_l[2]), .C(n27414), 
         .D(clock_flag_N_372), .Z(n27417)) /* synthesis lut_function=(!(A (B+!(C (D)))+!A !(B (C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(112[22:35])
    defparam i1_3_lut_4_lut_adj_380.init = 16'h6000;
    LUT4 i1_2_lut_3_lut_4_lut_adj_381 (.A(n29573), .B(n27779), .C(usart_recieve_state[2]), 
         .D(n3), .Z(n7)) /* synthesis lut_function=(A (B (C (D))+!B (C))+!A (C (D))) */ ;
    defparam i1_2_lut_3_lut_4_lut_adj_381.init = 16'hf020;
    LUT4 i1_2_lut_rep_325_4_lut (.A(n15384), .B(uart_data_R[1]), .C(n29684), 
         .D(uart_data_R[0]), .Z(n29601)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(224[28:46])
    defparam i1_2_lut_rep_325_4_lut.init = 16'hfeff;
    FD1P3IX usart_send_cnt_2266__i17 (.D(n148), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[17])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i17.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i16 (.D(n149), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[16])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i16.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i15 (.D(n150), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[15])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i15.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i14 (.D(n151), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[14])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i14.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i13 (.D(n152), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[13])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i13.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i12 (.D(n153), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[12])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i12.GSR = "ENABLED";
    LUT4 i2681_2_lut_3_lut_4_lut (.A(sec[2]), .B(n29695), .C(sec[4]), 
         .D(sec[3]), .Z(n43)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(97[16:24])
    defparam i2681_2_lut_3_lut_4_lut.init = 16'h78f0;
    LUT4 i1_4_lut_adj_382 (.A(n27417), .B(n2), .C(n29614), .D(key_bus_c_0), 
         .Z(n26525)) /* synthesis lut_function=(A+(B (C+(D))+!B !((D)+!C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(112[22:35])
    defparam i1_4_lut_adj_382.init = 16'heefa;
    FD1P3IX usart_send_cnt_2266__i11 (.D(n154), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[11])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i11.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i10 (.D(n155), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[10])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i10.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i9 (.D(n156), .SP(clk_1us_enable_43), .CD(n16676), 
            .CK(clk_1us), .Q(usart_send_cnt[9])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i9.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i8 (.D(n157), .SP(clk_1us_enable_43), .CD(n16676), 
            .CK(clk_1us), .Q(usart_send_cnt[8])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i8.GSR = "ENABLED";
    LUT4 i17726_3_lut (.A(n23732), .B(hour_h_u[0]), .C(time_set_flag), 
         .Z(n163)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(168[5:18])
    defparam i17726_3_lut.init = 16'hcaca;
    LUT4 i17725_4_lut (.A(n5), .B(n43_adj_1821), .C(hour_h[0]), .D(n6_adj_1841), 
         .Z(n23732)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+(D)))+!A (B+!(C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(70[10:16])
    defparam i17725_4_lut.init = 16'h3a30;
    LUT4 i2_3_lut_adj_383 (.A(n15687), .B(hour_h[2]), .C(hour_h[1]), .Z(n6_adj_1841)) /* synthesis lut_function=(!((B+(C))+!A)) */ ;
    defparam i2_3_lut_adj_383.init = 16'h0202;
    FD1P3IX usart_send_cnt_2266__i7 (.D(n158), .SP(clk_1us_enable_43), .CD(n16676), 
            .CK(clk_1us), .Q(usart_send_cnt[7])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i7.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i6 (.D(n159), .SP(clk_1us_enable_43), .CD(n16676), 
            .CK(clk_1us), .Q(usart_send_cnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i6.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i5 (.D(n160_adj_1810), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i5.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i4 (.D(n161_adj_1809), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i4.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i3 (.D(n162_adj_1811), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i3.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i2 (.D(n163_adj_1818), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i2.GSR = "ENABLED";
    FD1P3IX usart_send_cnt_2266__i1 (.D(n164), .SP(clk_1us_enable_43), .CD(n16676), 
            .CK(clk_1us), .Q(usart_send_cnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i1.GSR = "ENABLED";
    LUT4 cnt_1__bdd_3_lut (.A(cnt_adj_1865[1]), .B(cnt_adj_1865[2]), .C(cnt_adj_1865[0]), 
         .Z(n28732)) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A ((C)+!B))) */ ;
    defparam cnt_1__bdd_3_lut.init = 16'h2c2c;
    LUT4 cnt_0__bdd_3_lut_22399 (.A(cnt_adj_1865[0]), .B(cnt_adj_1865[1]), 
         .C(cnt_adj_1865[2]), .Z(n28744)) /* synthesis lut_function=(A (B+!(C))+!A ((C)+!B)) */ ;
    defparam cnt_0__bdd_3_lut_22399.init = 16'hdbdb;
    LUT4 i1_4_lut_adj_384 (.A(n14_adj_1815), .B(n27587), .C(n24), .D(usart_recieve_cnt[7]), 
         .Z(n26027)) /* synthesis lut_function=(A+(B (C+!(D))+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(203[17] 238[24])
    defparam i1_4_lut_adj_384.init = 16'hfaee;
    LUT4 i1_4_lut_adj_385 (.A(usart_recieve_state[1]), .B(usart_recieve_cnt[7]), 
         .C(n27579), .D(n29656), .Z(n14_adj_1815)) /* synthesis lut_function=(A (B (C+(D))+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(203[17] 238[24])
    defparam i1_4_lut_adj_385.init = 16'ha8a0;
    LUT4 i2_3_lut_adj_386 (.A(n27585), .B(n288), .C(usart_recieve_cnt[2]), 
         .Z(n27587)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(203[17] 238[24])
    defparam i2_3_lut_adj_386.init = 16'h0808;
    LUT4 i1_4_lut_adj_387 (.A(usart_recieve_cnt[7]), .B(n27576), .C(n288), 
         .D(n29606), .Z(n27579)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(203[17] 238[24])
    defparam i1_4_lut_adj_387.init = 16'hc088;
    LUT4 i5_4_lut (.A(n29678), .B(n7_adj_1817), .C(usart_recieve_cnt[6]), 
         .D(usart_recieve_cnt[5]), .Z(n27585)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(203[17] 238[24])
    defparam i5_4_lut.init = 16'h0004;
    LUT4 i1_4_lut_adj_388 (.A(n14_adj_1820), .B(n27630), .C(n24), .D(usart_recieve_cnt[6]), 
         .Z(n26265)) /* synthesis lut_function=(A+(B (C+!(D))+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(203[17] 238[24])
    defparam i1_4_lut_adj_388.init = 16'hfaee;
    LUT4 i3_4_lut_adj_389 (.A(usart_recieve_state[2]), .B(n21002), .C(usart_recieve_state[6]), 
         .D(n29649), .Z(n24)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ;
    defparam i3_4_lut_adj_389.init = 16'hff7f;
    LUT4 i1_2_lut_adj_390 (.A(hour_l_u[2]), .B(time_set_flag), .Z(n2)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(112[22:35])
    defparam i1_2_lut_adj_390.init = 16'h8888;
    LUT4 mux_51_i2_4_lut (.A(n72), .B(min_h_u[1]), .C(time_set_flag), 
         .D(n7921), .Z(n172)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(96[10] 124[8])
    defparam mux_51_i2_4_lut.init = 16'hc0ca;
    LUT4 i1_4_lut_adj_391 (.A(usart_recieve_state[1]), .B(usart_recieve_cnt[6]), 
         .C(n27581), .D(n29656), .Z(n14_adj_1820)) /* synthesis lut_function=(A (B (C+(D))+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(203[17] 238[24])
    defparam i1_4_lut_adj_391.init = 16'ha8a0;
    LUT4 i2_3_lut_adj_392 (.A(n27628), .B(n289), .C(usart_recieve_cnt[3]), 
         .Z(n27630)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(203[17] 238[24])
    defparam i2_3_lut_adj_392.init = 16'h0808;
    LUT4 mux_336_Mux_3_i31_3_lut (.A(n21256), .B(char_reg[3]), .C(n29576), 
         .Z(n2052)) /* synthesis lut_function=(A (B (C))+!A (B+!(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(117[20] 120[14])
    defparam mux_336_Mux_3_i31_3_lut.init = 16'hc5c5;
    LUT4 i1_4_lut_adj_393 (.A(usart_recieve_cnt[6]), .B(n27576), .C(n289), 
         .D(n29606), .Z(n27581)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(203[17] 238[24])
    defparam i1_4_lut_adj_393.init = 16'hc088;
    LUT4 i5_4_lut_adj_394 (.A(usart_recieve_cnt[4]), .B(n7_adj_1817), .C(usart_recieve_cnt[7]), 
         .D(n27879), .Z(n27628)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(163[10:29])
    defparam i5_4_lut_adj_394.init = 16'h0004;
    LUT4 i21735_2_lut (.A(usart_recieve_cnt[2]), .B(usart_recieve_cnt[5]), 
         .Z(n27879)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i21735_2_lut.init = 16'heeee;
    LUT4 i1_4_lut_adj_395 (.A(n27576), .B(n18), .C(usart_recieve_state[1]), 
         .D(n456), .Z(n26287)) /* synthesis lut_function=(A (B+(C (D)))+!A (B)) */ ;
    defparam i1_4_lut_adj_395.init = 16'heccc;
    LUT4 i1_4_lut_adj_396 (.A(n14_adj_1833), .B(n27646), .C(n24), .D(usart_recieve_cnt[4]), 
         .Z(n26551)) /* synthesis lut_function=(A+(B (C+!(D))+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(163[10:29])
    defparam i1_4_lut_adj_396.init = 16'hfaee;
    LUT4 i1_4_lut_adj_397 (.A(usart_recieve_state[1]), .B(usart_recieve_cnt[4]), 
         .C(n27584), .D(n29656), .Z(n14_adj_1833)) /* synthesis lut_function=(A (B (C+(D))+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(163[10:29])
    defparam i1_4_lut_adj_397.init = 16'ha8a0;
    LUT4 i2_3_lut_adj_398 (.A(n27644), .B(n291), .C(usart_recieve_cnt[5]), 
         .Z(n27646)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(163[10:29])
    defparam i2_3_lut_adj_398.init = 16'h0808;
    PFUMX min_l_2263_mux_6_i4 (.BLUT(min_l_3__N_195[3]), .ALUT(n22_adj_1829), 
          .C0(n2749), .Z(n28_adj_1831));
    LUT4 i14963_2_lut (.A(usart_recieve_state[1]), .B(usart_recieve_state[4]), 
         .Z(n21002)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i14963_2_lut.init = 16'heeee;
    LUT4 i1_4_lut_adj_399 (.A(usart_recieve_cnt[4]), .B(n27576), .C(n291), 
         .D(n29606), .Z(n27584)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(163[10:29])
    defparam i1_4_lut_adj_399.init = 16'hc088;
    LUT4 i5_4_lut_adj_400 (.A(usart_recieve_cnt[3]), .B(n7_adj_1817), .C(usart_recieve_cnt[7]), 
         .D(n27857), .Z(n27644)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;
    defparam i5_4_lut_adj_400.init = 16'h0004;
    LUT4 i21713_2_lut (.A(usart_recieve_cnt[6]), .B(usart_recieve_cnt[2]), 
         .Z(n27857)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i21713_2_lut.init = 16'heeee;
    LUT4 i1_4_lut_adj_401 (.A(n14_adj_1847), .B(n27629), .C(n24), .D(usart_recieve_cnt[3]), 
         .Z(n26493)) /* synthesis lut_function=(A+(B (C+!(D))+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(163[10:29])
    defparam i1_4_lut_adj_401.init = 16'hfaee;
    LUT4 i1_4_lut_adj_402 (.A(usart_recieve_state[1]), .B(usart_recieve_cnt[3]), 
         .C(n27583), .D(n29656), .Z(n14_adj_1847)) /* synthesis lut_function=(A (B (C+(D))+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(163[10:29])
    defparam i1_4_lut_adj_402.init = 16'ha8a0;
    LUT4 i2_3_lut_adj_403 (.A(n27628), .B(n292), .C(usart_recieve_cnt[6]), 
         .Z(n27629)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(163[10:29])
    defparam i2_3_lut_adj_403.init = 16'h0808;
    LUT4 i1_4_lut_adj_404 (.A(usart_recieve_cnt[3]), .B(n27576), .C(n292), 
         .D(n29606), .Z(n27583)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(163[10:29])
    defparam i1_4_lut_adj_404.init = 16'hc088;
    LUT4 i1_4_lut_adj_405 (.A(n14_adj_1816), .B(n27586), .C(n24), .D(usart_recieve_cnt[2]), 
         .Z(n26533)) /* synthesis lut_function=(A+(B (C+!(D))+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(203[17] 238[24])
    defparam i1_4_lut_adj_405.init = 16'hfaee;
    LUT4 i1_4_lut_adj_406 (.A(usart_recieve_state[1]), .B(usart_recieve_cnt[2]), 
         .C(n27577), .D(n29656), .Z(n14_adj_1816)) /* synthesis lut_function=(A (B (C+(D))+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(203[17] 238[24])
    defparam i1_4_lut_adj_406.init = 16'ha8a0;
    LUT4 i2_3_lut_adj_407 (.A(n27585), .B(n293), .C(usart_recieve_cnt[7]), 
         .Z(n27586)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(203[17] 238[24])
    defparam i2_3_lut_adj_407.init = 16'h0808;
    LUT4 i1_4_lut_adj_408 (.A(usart_recieve_cnt[2]), .B(n27576), .C(n293), 
         .D(n29606), .Z(n27577)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(203[17] 238[24])
    defparam i1_4_lut_adj_408.init = 16'hc088;
    LUT4 i2_4_lut (.A(usart_recieve_cnt[1]), .B(n22_adj_1813), .C(n24), 
         .D(n27597), .Z(n25285)) /* synthesis lut_function=(A (B+(C+(D)))+!A (B+(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(203[17] 238[24])
    defparam i2_4_lut.init = 16'hffec;
    PFUMX min_l_2263_mux_6_i2 (.BLUT(min_l_3__N_195[1]), .ALUT(n24_adj_1830), 
          .C0(n2749), .Z(n30));
    LUT4 i1_4_lut_adj_409 (.A(usart_recieve_state[1]), .B(n27580), .C(n29656), 
         .D(usart_recieve_cnt[1]), .Z(n22_adj_1813)) /* synthesis lut_function=(A (B+(C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(203[17] 238[24])
    defparam i1_4_lut_adj_409.init = 16'ha888;
    LUT4 i1_4_lut_adj_410 (.A(usart_recieve_cnt[1]), .B(n27576), .C(n294), 
         .D(n29606), .Z(n27580)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(43[5:17])
    defparam i1_4_lut_adj_410.init = 16'hc088;
    LUT4 mux_51_i3_4_lut (.A(n71), .B(min_h_u[2]), .C(time_set_flag), 
         .D(n7921), .Z(n171)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(96[10] 124[8])
    defparam mux_51_i3_4_lut.init = 16'hc0ca;
    LUT4 i1_4_lut_adj_411 (.A(uart_data_R[6]), .B(n18_adj_1819), .C(n7_adj_1808), 
         .D(n29609), .Z(usart_recieve_state_7__N_222[6])) /* synthesis lut_function=(A ((C+!(D))+!B)+!A ((C (D))+!B)) */ ;
    defparam i1_4_lut_adj_411.init = 16'hf3bb;
    LUT4 i1_4_lut_adj_412 (.A(uart_data_R[5]), .B(n18_adj_1819), .C(n7_adj_1806), 
         .D(n29609), .Z(usart_recieve_state_7__N_222[5])) /* synthesis lut_function=(A ((C+!(D))+!B)+!A ((C (D))+!B)) */ ;
    defparam i1_4_lut_adj_412.init = 16'hf3bb;
    LUT4 i1_4_lut_adj_413 (.A(uart_data_R[2]), .B(n18_adj_1819), .C(n7), 
         .D(n29609), .Z(usart_recieve_state_7__N_222[2])) /* synthesis lut_function=(A ((C+!(D))+!B)+!A ((C (D))+!B)) */ ;
    defparam i1_4_lut_adj_413.init = 16'hf3bb;
    LUT4 i1_4_lut_adj_414 (.A(uart_data_R[1]), .B(n18_adj_1819), .C(n3), 
         .D(n29609), .Z(usart_recieve_state_7__N_222[1])) /* synthesis lut_function=(A ((C+!(D))+!B)+!A ((C (D))+!B)) */ ;
    defparam i1_4_lut_adj_414.init = 16'hf3bb;
    LUT4 i1_4_lut_adj_415 (.A(n55), .B(n47), .C(n56), .D(usart_send_cnt[2]), 
         .Z(n16625)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_415.init = 16'hfefa;
    LUT4 i26_4_lut (.A(usart_send_cnt[16]), .B(n52), .C(n44_adj_1837), 
         .D(usart_send_cnt[15]), .Z(n55)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i26_4_lut.init = 16'hfffe;
    LUT4 i1_2_lut_adj_416 (.A(usart_send_cnt[1]), .B(usart_send_cnt[0]), 
         .Z(n47)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(246[11:25])
    defparam i1_2_lut_adj_416.init = 16'heeee;
    LUT4 i27_4_lut (.A(n35), .B(n54), .C(n48), .D(n36), .Z(n56)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i27_4_lut.init = 16'hfffe;
    LUT4 i23_4_lut (.A(usart_send_cnt[23]), .B(n46_adj_1836), .C(n32), 
         .D(usart_send_cnt[31]), .Z(n52)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i23_4_lut.init = 16'hfffe;
    LUT4 i15_3_lut (.A(usart_send_cnt[5]), .B(usart_send_cnt[4]), .C(usart_send_cnt[9]), 
         .Z(n44_adj_1837)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i15_3_lut.init = 16'hfefe;
    LUT4 i17_4_lut (.A(usart_send_cnt[30]), .B(usart_send_cnt[11]), .C(usart_send_cnt[13]), 
         .D(usart_send_cnt[3]), .Z(n46_adj_1836)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i17_4_lut.init = 16'hfffe;
    LUT4 i3_2_lut (.A(usart_send_cnt[8]), .B(usart_send_cnt[17]), .Z(n32)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i3_2_lut.init = 16'heeee;
    LUT4 i6_2_lut (.A(usart_send_cnt[27]), .B(usart_send_cnt[29]), .Z(n35)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i6_2_lut.init = 16'heeee;
    LUT4 i25_4_lut (.A(usart_send_cnt[28]), .B(n50), .C(n40), .D(usart_send_cnt[25]), 
         .Z(n54)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i25_4_lut.init = 16'hfffe;
    LUT4 i19_4_lut_adj_417 (.A(usart_send_cnt[19]), .B(usart_send_cnt[22]), 
         .C(usart_send_cnt[26]), .D(usart_send_cnt[21]), .Z(n48)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i19_4_lut_adj_417.init = 16'hfffe;
    LUT4 i7_2_lut (.A(usart_send_cnt[14]), .B(usart_send_cnt[7]), .Z(n36)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i7_2_lut.init = 16'heeee;
    FD1P3IX usart_send_cnt_2266__i0 (.D(n165_adj_1814), .SP(clk_1us_enable_43), 
            .CD(n16676), .CK(clk_1us), .Q(usart_send_cnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(291[119:138])
    defparam usart_send_cnt_2266__i0.GSR = "ENABLED";
    LUT4 i21_4_lut_adj_418 (.A(usart_send_cnt[20]), .B(usart_send_cnt[24]), 
         .C(usart_send_cnt[18]), .D(usart_send_cnt[6]), .Z(n50)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i21_4_lut_adj_418.init = 16'hfffe;
    LUT4 i11_2_lut (.A(usart_send_cnt[12]), .B(usart_send_cnt[10]), .Z(n40)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i11_2_lut.init = 16'heeee;
    LUT4 i22143_2_lut (.A(n31_adj_1807), .B(uart_clk), .Z(uart_clk_N_390)) /* synthesis lut_function=(A (B)+!A !(B)) */ ;
    defparam i22143_2_lut.init = 16'h9999;
    CCU2D add_88_5 (.A0(usart_recieve_cnt[3]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(usart_recieve_cnt[4]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24935), .COUT(n24936), .S0(n292), .S1(n291));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(207[82:104])
    defparam add_88_5.INIT0 = 16'h5aaa;
    defparam add_88_5.INIT1 = 16'h5aaa;
    defparam add_88_5.INJECT1_0 = "NO";
    defparam add_88_5.INJECT1_1 = "NO";
    LUT4 select_1838_Select_0_i5_3_lut (.A(uart_en_w), .B(usart_send_state[0]), 
         .C(usart_send_state[1]), .Z(uart_en_w_N_392)) /* synthesis lut_function=(A (B+(C))+!A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(269[9] 322[16])
    defparam select_1838_Select_0_i5_3_lut.init = 16'hecec;
    LUT4 i1_2_lut_adj_419 (.A(usart_send_state[0]), .B(clock_flag), .Z(n27541)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(269[9] 322[16])
    defparam i1_2_lut_adj_419.init = 16'h2222;
    LUT4 n14_bdd_4_lut (.A(cnt_adj_1865[3]), .B(cnt_adj_1865[2]), .C(cnt_adj_1865[0]), 
         .D(cnt_adj_1865[1]), .Z(n29417)) /* synthesis lut_function=(!(A+!(B (C (D)+!C !(D))+!B !(C (D))))) */ ;
    defparam n14_bdd_4_lut.init = 16'h4115;
    LUT4 i3_4_lut_adj_420 (.A(n29609), .B(n29610), .C(sys_rst_n_c), .D(n15687), 
         .Z(sys_clk_N_7_enable_28)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i3_4_lut_adj_420.init = 16'h0080;
    LUT4 i1_4_lut_adj_421 (.A(uart_cnt[15]), .B(n28034), .C(n10_adj_1838), 
         .D(n28032), .Z(n31_adj_1807)) /* synthesis lut_function=(A+((C+!(D))+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(259[8:27])
    defparam i1_4_lut_adj_421.init = 16'hfbff;
    LUT4 i21884_3_lut (.A(uart_cnt[5]), .B(n28004), .C(uart_cnt[2]), .Z(n28034)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i21884_3_lut.init = 16'h8080;
    LUT4 i4_4_lut_adj_422 (.A(uart_cnt[8]), .B(uart_cnt[14]), .C(uart_cnt[12]), 
         .D(uart_cnt[9]), .Z(n10_adj_1838)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(259[8:27])
    defparam i4_4_lut_adj_422.init = 16'hfffe;
    LUT4 i21882_4_lut (.A(uart_cnt[3]), .B(uart_cnt[7]), .C(uart_cnt[10]), 
         .D(n27963), .Z(n28032)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i21882_4_lut.init = 16'h8000;
    LUT4 i21856_4_lut (.A(uart_cnt[6]), .B(uart_cnt[13]), .C(uart_cnt[4]), 
         .D(uart_cnt[11]), .Z(n28004)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i21856_4_lut.init = 16'h8000;
    LUT4 i21815_2_lut (.A(uart_cnt[0]), .B(uart_cnt[1]), .Z(n27963)) /* synthesis lut_function=(A (B)) */ ;
    defparam i21815_2_lut.init = 16'h8888;
    PUR PUR_INST (.PUR(VCC_net));
    defparam PUR_INST.RST_PULSE = 1;
    LUT4 i114_4_lut (.A(usart_recieve_state[1]), .B(n27578), .C(usart_recieve_cnt[0]), 
         .D(n29656), .Z(n107)) /* synthesis lut_function=(A (B+(C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(163[10:29])
    defparam i114_4_lut.init = 16'ha888;
    LUT4 i10602_2_lut_4_lut (.A(clk_1us_enable_11), .B(usart_send_state[0]), 
         .C(clock_flag), .D(n16625), .Z(n16676)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(268[10] 323[8])
    defparam i10602_2_lut_4_lut.init = 16'h0800;
    LUT4 select_939_Select_6_i3_4_lut (.A(n1128), .B(n29668), .C(usart_send_state[0]), 
         .D(uart_data_w[6]), .Z(uart_data_w_7__N_345[6])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(269[9] 322[16])
    defparam select_939_Select_6_i3_4_lut.init = 16'heca0;
    LUT4 i14509_4_lut (.A(uart_data_w[6]), .B(clock_flag), .C(n4905), 
         .D(n16625), .Z(n1128)) /* synthesis lut_function=(A (B+(C+(D)))+!A (B+!((D)+!C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(289[22] 298[20])
    defparam i14509_4_lut.init = 16'heefc;
    LUT4 mux_336_Mux_7_i31_3_lut (.A(n28609), .B(char_reg[7]), .C(n29576), 
         .Z(n2048)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(117[20] 120[14])
    defparam mux_336_Mux_7_i31_3_lut.init = 16'hcaca;
    LUT4 i14778_4_lut (.A(usart_send_cnt[0]), .B(usart_send_cnt[2]), .C(temperature_data[6]), 
         .D(usart_send_cnt[1]), .Z(n4905)) /* synthesis lut_function=(!(A (B+!(C (D)))+!A (B+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(290[21] 297[28])
    defparam i14778_4_lut.init = 16'h2011;
    LUT4 i1_4_lut_adj_423 (.A(clock_flag), .B(n27426), .C(uart_data_w[5]), 
         .D(n16625), .Z(n8_adj_1842)) /* synthesis lut_function=(A+(B (C+!(D))+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(269[9] 322[16])
    defparam i1_4_lut_adj_423.init = 16'hfaee;
    LUT4 mux_336_Mux_6_i31_3_lut (.A(n28789), .B(char_reg[6]), .C(n29576), 
         .Z(n2049)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(117[20] 120[14])
    defparam mux_336_Mux_6_i31_3_lut.init = 16'hcaca;
    LUT4 i14511_4_lut (.A(uart_data_w[4]), .B(clock_flag), .C(n4907), 
         .D(n16625), .Z(n1130)) /* synthesis lut_function=(A (B+(C+(D)))+!A (B+!((D)+!C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(289[22] 298[20])
    defparam i14511_4_lut.init = 16'heefc;
    LUT4 i14776_4_lut (.A(usart_send_cnt[0]), .B(usart_send_cnt[2]), .C(temperature_data[4]), 
         .D(usart_send_cnt[1]), .Z(n4907)) /* synthesis lut_function=(A (B+(C (D)))+!A (B+!(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(290[21] 297[28])
    defparam i14776_4_lut.init = 16'hecdd;
    LUT4 i1_4_lut_adj_424 (.A(n29668), .B(n8_adj_1839), .C(uart_data_w[3]), 
         .D(n27541), .Z(uart_data_w_7__N_345[3])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(269[9] 322[16])
    defparam i1_4_lut_adj_424.init = 16'heca0;
    LUT4 i2_3_lut_rep_319_4_lut (.A(n29688), .B(usart_recieve_state[1]), 
         .C(usart_recieve_state[0]), .D(n29675), .Z(n29595)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i2_3_lut_rep_319_4_lut.init = 16'h0002;
    LUT4 i21_4_lut_adj_425 (.A(temperature_data[3]), .B(uart_data_w[3]), 
         .C(n16625), .D(n29669), .Z(n8_adj_1839)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(269[9] 322[16])
    defparam i21_4_lut_adj_425.init = 16'hcac0;
    LUT4 mux_1388_i3_4_lut (.A(uart_data_w[2]), .B(n4899), .C(n16625), 
         .D(usart_send_cnt[2]), .Z(n4919)) /* synthesis lut_function=(A (B+(C+(D)))+!A !(B (C)+!B (C+!(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(290[21] 297[28])
    defparam mux_1388_i3_4_lut.init = 16'hafac;
    LUT4 mux_1384_i3_4_lut (.A(usart_send_cnt[0]), .B(temperature_data[10]), 
         .C(usart_send_cnt[1]), .D(temperature_data[2]), .Z(n4899)) /* synthesis lut_function=(A (C (D))+!A (B+!(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(290[21] 297[28])
    defparam mux_1384_i3_4_lut.init = 16'he545;
    LUT4 mux_1388_i2_4_lut (.A(uart_data_w[1]), .B(n4900), .C(n16625), 
         .D(usart_send_cnt[2]), .Z(n4920)) /* synthesis lut_function=(A (B+(C+(D)))+!A !(B (C)+!B (C+!(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(290[21] 297[28])
    defparam mux_1388_i2_4_lut.init = 16'hafac;
    LUT4 i14779_4_lut (.A(temperature_data[9]), .B(usart_send_cnt[1]), .C(temperature_data[1]), 
         .D(usart_send_cnt[0]), .Z(n4900)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(290[21] 297[28])
    defparam i14779_4_lut.init = 16'hc088;
    LUT4 i1_3_lut_4_lut_adj_426 (.A(usart_recieve_cnt[2]), .B(n29678), .C(n21236), 
         .D(n29680), .Z(n27779)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i1_3_lut_4_lut_adj_426.init = 16'hfffe;
    LUT4 i2_3_lut_4_lut_adj_427 (.A(usart_recieve_cnt[2]), .B(n29678), .C(n17), 
         .D(n29661), .Z(sys_clk_N_7_enable_33)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;
    defparam i2_3_lut_4_lut_adj_427.init = 16'h1000;
    PFUMX i25 (.BLUT(n27645), .ALUT(n13), .C0(usart_recieve_cnt[5]), .Z(n18));
    PFUMX hour_l_2264_mux_6_i4 (.BLUT(n165), .ALUT(n22_adj_1827), .C0(n2735), 
          .Z(n28));
    FD1S3AY DS18B20_rst_248 (.D(DS18B20_rst_N_367), .CK(clock), .Q(DS18B20_rst)) /* synthesis lse_init_val=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(60[10] 65[8])
    defparam DS18B20_rst_248.GSR = "DISABLED";
    LUT4 i4_4_lut_adj_428 (.A(sys_clk_N_7_enable_57), .B(n27404), .C(usart_recieve_state[5]), 
         .D(n6), .Z(n75_adj_1835)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i4_4_lut_adj_428.init = 16'h0800;
    LUT4 i3_4_lut_adj_429 (.A(n26), .B(usart_recieve_state[4]), .C(n21236), 
         .D(n29627), .Z(n27404)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(201[18] 239[16])
    defparam i3_4_lut_adj_429.init = 16'h0800;
    LUT4 i1_4_lut_adj_430 (.A(usart_recieve_cnt[0]), .B(n27576), .C(n295), 
         .D(n29606), .Z(n27578)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i1_4_lut_adj_430.init = 16'hc088;
    LUT4 i1_2_lut_adj_431 (.A(time_set_ready_flag), .B(time_set_flag_N_377), 
         .Z(sys_clk_N_7_enable_8)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i1_2_lut_adj_431.init = 16'heeee;
    LUT4 i3_4_lut_adj_432 (.A(usart_recieve_state[5]), .B(n27779), .C(n29610), 
         .D(n29573), .Z(time_set_flag_N_377)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i3_4_lut_adj_432.init = 16'h8000;
    LUT4 i1_2_lut_rep_295_3_lut_4_lut (.A(n26), .B(n29656), .C(usart_recieve_state[1]), 
         .D(n29688), .Z(n29571)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(187[10] 241[8])
    defparam i1_2_lut_rep_295_3_lut_4_lut.init = 16'h2000;
    LUT4 i10_4_lut (.A(temp_data[4]), .B(n20), .C(n16), .D(temp_data[8]), 
         .Z(clock_enable_21)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(432[8:20])
    defparam i10_4_lut.init = 16'hfffe;
    \uart_recv(CLK_FREQ=12000000,UART_BPS=115200)  u_uart_recv (.sys_clk_c(sys_clk_c), 
            .rx_flag(rx_flag), .uart_en_R(uart_en_R), .uart_rx_bus_c(uart_rx_bus_c), 
            .sys_clk_c_enable_47(sys_clk_c_enable_47), .n31(n31), .n29636(n29636), 
            .GND_net(GND_net), .uart_data_R({uart_data_R}), .n29575(n29575)) /* synthesis syn_module_defined=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(339[1] 347[6])
    LUT4 i9_4_lut (.A(temp_data[6]), .B(n18_adj_1845), .C(temp_data[3]), 
         .D(temp_data[10]), .Z(n20)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(432[8:20])
    defparam i9_4_lut.init = 16'hfffe;
    LUT4 i5_2_lut (.A(temp_data[1]), .B(temp_data[5]), .Z(n16)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(432[8:20])
    defparam i5_2_lut.init = 16'heeee;
    LUT4 i7_4_lut (.A(temp_data[7]), .B(temp_data[2]), .C(temp_data[9]), 
         .D(temp_data[0]), .Z(n18_adj_1845)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(432[8:20])
    defparam i7_4_lut.init = 16'hfffe;
    TSALL TSALL_INST (.TSALL(GND_net));
    GSR GSR_INST (.GSR(sys_rst_n_c));
    PLL u_pll (.sys_clk_c(sys_clk_c), .clk_1us(clk_1us), .GND_net(GND_net)) /* synthesis NGD_DRC_MASK=1, syn_module_defined=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(366[5] 369[2])
    LUT4 i2_4_lut_adj_433 (.A(n27598), .B(n107), .C(usart_recieve_cnt[0]), 
         .D(n24), .Z(n25348)) /* synthesis lut_function=(A+(B+(C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(163[10:29])
    defparam i2_4_lut_adj_433.init = 16'hfeee;
    PFUMX i22791 (.BLUT(n29729), .ALUT(n29730), .C0(n2749), .Z(n29731));
    PFUMX i22400 (.BLUT(n28788), .ALUT(n28787), .C0(cnt_adj_1865[4]), 
          .Z(n28789));
    OLED12832 OLED_DRIVER (.sys_clk_c(sys_clk_c), .\cnt_main[0] (cnt_main[0]), 
            .char_reg({char_reg[7:6], Open_0, Open_1, Open_2, Open_3, 
            Open_4, Open_5}), .cnt({Open_6, Open_7, Open_8, Open_9, 
            Open_10, Open_11, Open_12, Open_13, Open_14, Open_15, 
            Open_16, cnt_adj_1865[4:3], Open_17, Open_18, Open_19}), 
            .n29576(n29576), .\char_reg[3] (char_reg[3]), .\char_reg[2] (char_reg[2]), 
            .\char_reg[1] (char_reg[1]), .sign(sign), .min_h({min_h}), 
            .min_l({min_l}), .OLED_bus_c_4(OLED_bus_c_4), .OLED_bus_c_3(OLED_bus_c_3), 
            .n29583(n29583), .n29584(n29584), .n29582(n29582), .OLED_bus_c_1(OLED_bus_c_1), 
            .n29418(n29418), .n29564(n29564), .temp_l({temp_l}), .temp_p({temp_p}), 
            .temp_h({temp_h}), .OLED_bus_c_0(OLED_bus_c_0), .OLED_bus_c_2(OLED_bus_c_2), 
            .n1767(n1767), .n2523(n2523), .n1389(n1389), .n2145(n2145), 
            .\hour_h[2] (hour_h[2]), .\hour_l[2] (hour_l[2]), .n1011(n1011), 
            .n4(n4), .GND_net(GND_net), .\cnt[1] (cnt_adj_1865[1]), .\cnt[2] (cnt_adj_1865[2]), 
            .\cnt[0] (cnt_adj_1865[0]), .n1013(n1013), .n1014(n1014), 
            .n1392(n1392), .n2148(n2148), .n1770(n1770), .n2526(n2526), 
            .n22(n22), .n2054(n2054), .\hour_h[0] (hour_h[0]), .\hour_l[0] (hour_l[0]), 
            .n28744(n28744), .n2048(n2048), .n2147(n2147), .n2525(n2525), 
            .n1391(n1391), .n1769(n1769), .n1012(n1012), .n1015(n1015), 
            .n846(n846), .n1393(n1393), .n1771(n1771), .\hour_h[3] (hour_h[3]), 
            .\hour_l[3] (hour_l[3]), .n1390(n1390), .n1768(n1768), .n2146(n2146), 
            .n2524(n2524), .n2149(n2149), .n2527(n2527), .n11(n11), 
            .n2150(n2150), .n2528(n2528), .n2151(n2151), .n2529(n2529), 
            .n1017(n1017), .n1016(n1016), .n29562(n29562), .n2052(n2052), 
            .n22_adj_1(n22_adj_1812), .n2053(n2053), .n28732(n28732), 
            .n2049(n2049), .n29563(n29563), .n1394(n1394), .n1772(n1772), 
            .n1395(n1395), .n1773(n1773)) /* synthesis syn_module_defined=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(479[11] 497[2])
    CCU2D uart_cnt_2265_add_4_17 (.A0(uart_cnt[15]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n24967), .S0(n70_adj_1823));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265_add_4_17.INIT0 = 16'hfaaa;
    defparam uart_cnt_2265_add_4_17.INIT1 = 16'h0000;
    defparam uart_cnt_2265_add_4_17.INJECT1_0 = "NO";
    defparam uart_cnt_2265_add_4_17.INJECT1_1 = "NO";
    divide u1_divide (.GND_net(GND_net), .sys_clk_c(sys_clk_c), .sys_clk_N_7(sys_clk_N_7), 
           .sys_rst_n_c(sys_rst_n_c), .clock(clock)) /* synthesis syn_module_defined=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(420[8] 424[2])
    \uart_send(CLK_FREQ=12000000,UART_BPS=115200)  u_uart_send (.sys_clk_c(sys_clk_c), 
            .\usart_send_state_31__N_281[1] (usart_send_state_31__N_281[1]), 
            .uart_en_w(uart_en_w), .uart_tx_bus_c(uart_tx_bus_c), .n29694(n29694), 
            .\usart_send_state[1] (usart_send_state[1]), .usart_send_state_31__N_277(usart_send_state_31__N_277), 
            .n29668(n29668), .uart_data_w({uart_data_w}), .\usart_send_cnt[2] (usart_send_cnt[2]), 
            .\usart_send_cnt[1] (usart_send_cnt[1]), .\usart_send_cnt[0] (usart_send_cnt[0]), 
            .n29669(n29669), .\temperature_data[5] (temperature_data[5]), 
            .n27426(n27426), .sys_clk_c_enable_77(sys_clk_c_enable_77), 
            .n16624(n16624), .GND_net(GND_net), .n8730(n8730), .n27541(n27541), 
            .\uart_data_w_7__N_345[7] (uart_data_w_7__N_345[7]), .\temperature_data[7] (temperature_data[7]), 
            .n16625(n16625), .\usart_send_state[0] (usart_send_state[0]), 
            .n8(n8_adj_1842), .\uart_data_w_7__N_345[5] (uart_data_w_7__N_345[5]), 
            .n1130(n1130), .\uart_data_w_7__N_345[4] (uart_data_w_7__N_345[4]), 
            .n4919(n4919), .clock_flag(clock_flag), .\uart_data_w_7__N_345[2] (uart_data_w_7__N_345[2]), 
            .n4920(n4920), .\uart_data_w_7__N_345[1] (uart_data_w_7__N_345[1])) /* synthesis syn_module_defined=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(352[1] 360[6])
    Beeper u1_beep (.BEEP_bus_c(BEEP_bus_c), .sys_clk_c(sys_clk_c), .Beep_status_uart({Beep_status_uart}), 
           .sys_rst_n_c(sys_rst_n_c), .GND_net(GND_net), .VCC_net(VCC_net), 
           .beep_en_reg(beep_en_reg)) /* synthesis syn_module_defined=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(408[9] 415[2])
    CCU2D uart_cnt_2265_add_4_15 (.A0(uart_cnt[13]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(uart_cnt[14]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24966), .COUT(n24967), .S0(n72_adj_1825), 
          .S1(n71_adj_1824));   // f:/git/my/fpga/training_v2.0/code/core/controller.v(258[16:29])
    defparam uart_cnt_2265_add_4_15.INIT0 = 16'hfaaa;
    defparam uart_cnt_2265_add_4_15.INIT1 = 16'hfaaa;
    defparam uart_cnt_2265_add_4_15.INJECT1_0 = "NO";
    defparam uart_cnt_2265_add_4_15.INJECT1_1 = "NO";
    
endmodule
//
// Verilog Description of module ds18b20_dri
//

module ds18b20_dri (clk_1us, DS18B20_rst, dq_N_756, sign, \temp_data[0] , 
            DS18B20_bus_out, GND_net, \temp_data[10] , \temp_data[9] , 
            \temp_data[8] , \temp_data[7] , \temp_data[6] , \temp_data[5] , 
            \temp_data[4] , \temp_data[3] , \temp_data[2] , \temp_data[1] , 
            n8566) /* synthesis syn_module_defined=1 */ ;
    input clk_1us;
    input DS18B20_rst;
    output dq_N_756;
    output sign;
    output \temp_data[0] ;
    input DS18B20_bus_out;
    input GND_net;
    output \temp_data[10] ;
    output \temp_data[9] ;
    output \temp_data[8] ;
    output \temp_data[7] ;
    output \temp_data[6] ;
    output \temp_data[5] ;
    output \temp_data[4] ;
    output \temp_data[3] ;
    output \temp_data[2] ;
    output \temp_data[1] ;
    output n8566;
    
    wire clk_1us /* synthesis SET_AS_NETWORK=clk_1us, is_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(368[14:21])
    wire [4:0]bit_width;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(56[24:33])
    wire [4:0]rd_cnt;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(54[24:30])
    wire [15:0]n33;
    wire [15:0]rd_data;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(57[24:31])
    wire [15:0]n399;
    wire [15:0]org_data;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(58[24:32])
    
    wire n21294, n29644, n9;
    wire [3:0]flow_cnt;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(52[24:32])
    
    wire n29662, n13250, n7448, n29619;
    wire [15:0]org_data_15__N_714;
    
    wire n29605, n2128, n29604, n2110, n29558;
    wire [3:0]wr_cnt;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(53[24:30])
    
    wire n29663, n29618, n4;
    wire [19:0]cnt_1us;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(49[24:31])
    
    wire n29607, n29645, n6, rst_n_N_535;
    wire [3:0]flow_cnt_3__N_577;
    wire [15:0]rd_data_15__N_603;
    wire [2:0]next_state_2__N_574;
    
    wire init_done_N_760, cnt_1us_en, cnt_1us_en_N_770, dq_N_792;
    wire [2:0]next_state_2__N_565;
    
    wire st_done_N_764;
    wire [4:0]rd_cnt_4__N_585;
    wire [3:0]wr_cnt_3__N_581;
    wire [3:0]cmd_cnt;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(60[24:31])
    wire [3:0]cmd_cnt_3__N_646;
    wire [10:0]data1;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(59[24:29])
    wire [10:0]data1_10__N_635;
    
    wire n29556, n9572, n13252, n39, n30946, n27891, dq_N_809, 
        n2, n15713, n15754, n29579, n29713, n29714, n29643;
    wire [3:0]flow_cnt_3__N_673;
    
    wire n29549, n29539;
    wire [7:0]n2095;
    
    wire n9513, n29542, n8456, n39_adj_1785, n29642;
    wire [0:0]n4974;
    
    wire n29540;
    wire [7:0]wr_data;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(55[24:31])
    
    wire n1, n2122, n2125, n29585, n29720, n29721, n2113, n29586, 
        n29565, n29541, n15832, n30947, n27897, n29600, n15958, 
        n15836, n28173, n28174, dq_N_797, n15839, n5, n3, n21264, 
        n7446, n27571, n2131, n29552, n7577, n21375, n27383, n29693, 
        n7;
    wire [19:0]n107;
    
    wire n6_adj_1786, n6_adj_1787;
    wire [10:0]n642;
    
    wire n24938, n24942, n21329, dq_N_757, dq_N_800, dq_N_811, n15859, 
        n29696, n20687, n30948, n4_adj_1788, n15760, n27699, n29550, 
        n27735, n24941, n29698, n27736, n7488, n28080, n29716, 
        n29620, n28798, n28799, n5_adj_1789, n4_adj_1790, n29700, 
        n21242, n16451, n2_adj_1791, n15774;
    wire [19:0]n85;
    wire [7:0]wr_data_7__N_730;
    
    wire n27765;
    wire [15:0]rd_data_15__N_685;
    
    wire n15071, n15156, n29659, n25525, n29578, n27965, n30933, 
        n26651, n8, cnt_1us_en_N_787, n27529, n5_adj_1792, n3_adj_1793, 
        n29577, n16641, st_done_N_781;
    wire [0:0]n5016;
    
    wire n25277, n28024, n29657, n15969, n29545, n7447, n27881, 
        n4_adj_1794, n27530, n27531, n27606, n4_adj_1795, n21210, 
        n21345, n29559, n4_adj_1796;
    wire [3:0]n5028;
    
    wire n29602, n15812, n24986, n24985;
    wire [3:0]n4960;
    wire [0:0]n4982;
    
    wire n29603, n4_adj_1797, n27700, n24940, n24984, n24983;
    wire [3:0]cmd_cnt_3__N_710;
    
    wire n8_adj_1798, n24982, n27422, n24981, n24980, n24979, n24978, 
        n7449, n5_adj_1799, n24977;
    wire [3:0]n4461;
    
    wire n4_adj_1800, dq_N_813, n27889, n28052, n5_adj_1801, n3_adj_1802, 
        n24939, n5_adj_1803, n3_adj_1804, n4_adj_1805, n8902;
    
    LUT4 mux_117_i16_3_lut_4_lut (.A(bit_width[4]), .B(rd_cnt[4]), .C(n33[15]), 
         .D(rd_data[15]), .Z(n399[15])) /* synthesis lut_function=(A (B (D)+!B (C))+!A (D)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(278[20:38])
    defparam mux_117_i16_3_lut_4_lut.init = 16'hfd20;
    LUT4 mux_117_i11_3_lut_4_lut (.A(bit_width[4]), .B(rd_cnt[4]), .C(org_data[10]), 
         .D(rd_data[10]), .Z(n399[10])) /* synthesis lut_function=(A (B (D)+!B (C))+!A (D)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(278[20:38])
    defparam mux_117_i11_3_lut_4_lut.init = 16'hfd20;
    LUT4 i2_3_lut_4_lut (.A(bit_width[4]), .B(rd_cnt[4]), .C(n21294), 
         .D(n29644), .Z(n9)) /* synthesis lut_function=((B+((D)+!C))+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(278[20:38])
    defparam i2_3_lut_4_lut.init = 16'hffdf;
    LUT4 i14594_2_lut_rep_386 (.A(flow_cnt[0]), .B(flow_cnt[1]), .Z(n29662)) /* synthesis lut_function=(A (B)) */ ;
    defparam i14594_2_lut_rep_386.init = 16'h8888;
    LUT4 i7493_3_lut_3_lut_4_lut (.A(flow_cnt[0]), .B(flow_cnt[1]), .C(n13250), 
         .D(flow_cnt[2]), .Z(n7448)) /* synthesis lut_function=(A (B (C (D)+!C !(D))+!B (D))+!A (D)) */ ;
    defparam i7493_3_lut_3_lut_4_lut.init = 16'hf708;
    LUT4 i2802_3_lut_rep_343_4_lut (.A(flow_cnt[0]), .B(flow_cnt[1]), .C(flow_cnt[2]), 
         .D(flow_cnt[3]), .Z(n29619)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;
    defparam i2802_3_lut_rep_343_4_lut.init = 16'h7f80;
    FD1P3AX org_data_i0_i0 (.D(org_data_15__N_714[0]), .SP(DS18B20_rst), 
            .CK(clk_1us), .Q(org_data[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam org_data_i0_i0.GSR = "DISABLED";
    LUT4 i1_2_lut_rep_282_4_lut (.A(n29605), .B(n2128), .C(n29604), .D(n2110), 
         .Z(n29558)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_2_lut_rep_282_4_lut.init = 16'hfffe;
    LUT4 i2761_2_lut_rep_387 (.A(wr_cnt[1]), .B(wr_cnt[0]), .Z(n29663)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(249[39:52])
    defparam i2761_2_lut_rep_387.init = 16'h8888;
    LUT4 i1_3_lut_4_lut (.A(wr_cnt[1]), .B(wr_cnt[0]), .C(wr_cnt[2]), 
         .D(n29618), .Z(n4)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(249[39:52])
    defparam i1_3_lut_4_lut.init = 16'h8000;
    LUT4 i1_2_lut_3_lut_4_lut (.A(cnt_1us[19]), .B(n29607), .C(n29645), 
         .D(cnt_1us[5]), .Z(n6)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(189[28:45])
    defparam i1_2_lut_3_lut_4_lut.init = 16'hffef;
    FD1S3DX flow_cnt_i0 (.D(flow_cnt_3__N_577[0]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(flow_cnt[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam flow_cnt_i0.GSR = "DISABLED";
    FD1S3DX rd_data_i0 (.D(rd_data_15__N_603[0]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(rd_data[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam rd_data_i0.GSR = "DISABLED";
    FD1S3DX init_done_194 (.D(init_done_N_760), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(next_state_2__N_574[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam init_done_194.GSR = "DISABLED";
    FD1S3BX cnt_1us_en_195 (.D(cnt_1us_en_N_770), .CK(clk_1us), .PD(rst_n_N_535), 
            .Q(cnt_1us_en)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam cnt_1us_en_195.GSR = "DISABLED";
    FD1S3DX dq_out_196 (.D(dq_N_792), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(dq_N_756)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam dq_out_196.GSR = "DISABLED";
    FD1S3DX st_done_197 (.D(st_done_N_764), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(next_state_2__N_565[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam st_done_197.GSR = "DISABLED";
    FD1S3DX rd_cnt_i0 (.D(rd_cnt_4__N_585[0]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(rd_cnt[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam rd_cnt_i0.GSR = "DISABLED";
    FD1S3DX wr_cnt_i0 (.D(wr_cnt_3__N_581[0]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(wr_cnt[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam wr_cnt_i0.GSR = "DISABLED";
    FD1S3DX cmd_cnt_i0 (.D(cmd_cnt_3__N_646[0]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cmd_cnt[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam cmd_cnt_i0.GSR = "DISABLED";
    FD1S3DX sign_206 (.D(n33[15]), .CK(clk_1us), .CD(rst_n_N_535), .Q(sign)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(321[10] 328[8])
    defparam sign_206.GSR = "DISABLED";
    FD1S3DX data1_i0 (.D(data1_10__N_635[0]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(data1[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(321[10] 328[8])
    defparam data1_i0.GSR = "DISABLED";
    FD1S3DX temp_data_i1 (.D(data1[0]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(\temp_data[0] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(344[9:28])
    defparam temp_data_i1.GSR = "DISABLED";
    LUT4 i7496_3_lut_4_lut (.A(n29556), .B(flow_cnt[0]), .C(flow_cnt[1]), 
         .D(n9572), .Z(n13252)) /* synthesis lut_function=(A (B (C (D))+!B ((D)+!C))+!A ((D)+!C)) */ ;
    defparam i7496_3_lut_4_lut.init = 16'hf707;
    LUT4 flow_cnt_1__bdd_4_lut (.A(flow_cnt[1]), .B(n39), .C(flow_cnt[0]), 
         .D(n30946), .Z(n27891)) /* synthesis lut_function=(A+(B (C+(D))+!B (D))) */ ;
    defparam flow_cnt_1__bdd_4_lut.init = 16'hffea;
    LUT4 mux_1398_Mux_0_i2_3_lut (.A(dq_N_809), .B(DS18B20_bus_out), .C(flow_cnt[0]), 
         .Z(n2)) /* synthesis lut_function=(A (B (C))+!A (B+!(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(184[17] 220[24])
    defparam mux_1398_Mux_0_i2_3_lut.init = 16'hc5c5;
    LUT4 i1_2_lut_rep_303_3_lut (.A(n15713), .B(n15754), .C(cnt_1us[19]), 
         .Z(n29579)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(241[37:53])
    defparam i1_2_lut_rep_303_3_lut.init = 16'hfefe;
    PFUMX i22783 (.BLUT(n29713), .ALUT(n29714), .C0(n29643), .Z(flow_cnt_3__N_673[1]));
    LUT4 i2970_2_lut_rep_263_3_lut_4_lut (.A(n29549), .B(rd_cnt[0]), .C(rd_cnt[2]), 
         .D(rd_cnt[1]), .Z(n29539)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(279[21] 302[28])
    defparam i2970_2_lut_rep_263_3_lut_4_lut.init = 16'h4000;
    LUT4 reduce_or_380_i2_2_lut (.A(n2095[7]), .B(n2095[5]), .Z(n9513)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam reduce_or_380_i2_2_lut.init = 16'heeee;
    LUT4 i2977_2_lut_3_lut_4_lut (.A(rd_cnt[1]), .B(n29542), .C(rd_cnt[3]), 
         .D(rd_cnt[2]), .Z(n8456)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(279[21] 302[28])
    defparam i2977_2_lut_3_lut_4_lut.init = 16'h8000;
    LUT4 mux_1406_i1_3_lut (.A(cnt_1us_en), .B(n39_adj_1785), .C(n29642), 
         .Z(n4974[0])) /* synthesis lut_function=(A (B+!(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(184[17] 220[24])
    defparam mux_1406_i1_3_lut.init = 16'h8a8a;
    LUT4 flow_cnt_3__I_0_233_i6_2_lut_rep_437 (.A(flow_cnt[2]), .B(flow_cnt[3]), 
         .Z(n30946)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(292[25:29])
    defparam flow_cnt_3__I_0_233_i6_2_lut_rep_437.init = 16'heeee;
    LUT4 i2963_2_lut_rep_264_3_lut_4_lut (.A(n21294), .B(n29644), .C(rd_cnt[1]), 
         .D(rd_cnt[0]), .Z(n29540)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;
    defparam i2963_2_lut_rep_264_3_lut_4_lut.init = 16'h2000;
    LUT4 i14417_2_lut (.A(wr_data[1]), .B(wr_cnt[0]), .Z(n1)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(240[51:57])
    defparam i14417_2_lut.init = 16'h8888;
    LUT4 i2954_2_lut_rep_266_3_lut (.A(n21294), .B(n29644), .C(rd_cnt[0]), 
         .Z(n29542)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;
    defparam i2954_2_lut_rep_266_3_lut.init = 16'h2020;
    LUT4 select_558_Select_0_i10_2_lut_rep_309 (.A(n2122), .B(n2125), .Z(n29585)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam select_558_Select_0_i10_2_lut_rep_309.init = 16'heeee;
    FD1S3BX cur_state_FSM_i1 (.D(n2110), .CK(clk_1us), .PD(rst_n_N_535), 
            .Q(n2095[1]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam cur_state_FSM_i1.GSR = "DISABLED";
    PFUMX i22787 (.BLUT(n29720), .ALUT(n29721), .C0(cmd_cnt[0]), .Z(cmd_cnt_3__N_646[1]));
    LUT4 i2_3_lut_rep_289_4_lut (.A(n2122), .B(n2125), .C(n2113), .D(n29586), 
         .Z(n29565)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i2_3_lut_rep_289_4_lut.init = 16'hfffe;
    LUT4 i1_2_lut_rep_265 (.A(flow_cnt[0]), .B(n39), .Z(n29541)) /* synthesis lut_function=((B)+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i1_2_lut_rep_265.init = 16'hdddd;
    LUT4 i4_2_lut_3_lut (.A(n2122), .B(n2125), .C(n2128), .Z(n15832)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i4_2_lut_3_lut.init = 16'hfefe;
    LUT4 i3002_2_lut_3_lut_4_lut_else_4_lut (.A(cmd_cnt[2]), .Z(n30947)) /* synthesis lut_function=(A) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(254[22] 259[20])
    defparam i3002_2_lut_3_lut_4_lut_else_4_lut.init = 16'haaaa;
    LUT4 i14598_2_lut_rep_324_4_lut (.A(cmd_cnt[2]), .B(wr_cnt[3]), .C(n27897), 
         .D(cmd_cnt[0]), .Z(n29600)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A (D)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(254[22] 259[20])
    defparam i14598_2_lut_rep_324_4_lut.init = 16'hf700;
    LUT4 i1_2_lut_3_lut_4_lut_adj_255 (.A(n29618), .B(n2110), .C(wr_data[1]), 
         .D(n29605), .Z(n15958)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_2_lut_3_lut_4_lut_adj_255.init = 16'hf0e0;
    LUT4 i1_2_lut_3_lut_4_lut_adj_256 (.A(n29618), .B(n2110), .C(wr_data[4]), 
         .D(n29605), .Z(n15836)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_2_lut_3_lut_4_lut_adj_256.init = 16'hf0e0;
    L6MUX21 i22024 (.D0(n28173), .D1(n28174), .SD(wr_cnt[2]), .Z(dq_N_797));
    LUT4 rst_n_I_0_1_lut (.A(DS18B20_rst), .Z(rst_n_N_535)) /* synthesis lut_function=(!(A)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(341[8:14])
    defparam rst_n_I_0_1_lut.init = 16'h5555;
    LUT4 i1_2_lut_3_lut_4_lut_adj_257 (.A(n29618), .B(n2110), .C(wr_data[5]), 
         .D(n29605), .Z(n15839)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_2_lut_3_lut_4_lut_adj_257.init = 16'hf0e0;
    LUT4 i3_4_lut (.A(n5), .B(n3), .C(flow_cnt[0]), .D(n15832), .Z(flow_cnt_3__N_577[0])) /* synthesis lut_function=(A+(B+(C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i3_4_lut.init = 16'hfeee;
    LUT4 i1_4_lut_rep_280 (.A(cnt_1us[2]), .B(n29579), .C(n21264), .D(cnt_1us[3]), 
         .Z(n29556)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i1_4_lut_rep_280.init = 16'hfcec;
    LUT4 i1_4_lut (.A(n7446), .B(flow_cnt_3__N_673[0]), .C(n27571), .D(n2131), 
         .Z(n5)) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut.init = 16'heca0;
    LUT4 select_559_Select_0_i3_4_lut (.A(n29552), .B(n29618), .C(flow_cnt[0]), 
         .D(n7577), .Z(n3)) /* synthesis lut_function=(A (B (C (D)))+!A (B (C (D)+!C !(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam select_559_Select_0_i3_4_lut.init = 16'hc004;
    LUT4 mux_113_i1_4_lut (.A(n29643), .B(flow_cnt[0]), .C(n21375), .D(n39), 
         .Z(flow_cnt_3__N_673[0])) /* synthesis lut_function=(!(A ((C)+!B)+!A !(B ((D)+!C)+!B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(304[22] 308[20])
    defparam mux_113_i1_4_lut.init = 16'h5c1c;
    LUT4 i4_4_lut (.A(cnt_1us[0]), .B(n27383), .C(cnt_1us[8]), .D(n6), 
         .Z(n39)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i4_4_lut.init = 16'hfffe;
    LUT4 i14627_2_lut_rep_417 (.A(cnt_1us[8]), .B(cnt_1us[5]), .Z(n29693)) /* synthesis lut_function=(A (B)) */ ;
    defparam i14627_2_lut_rep_417.init = 16'h8888;
    LUT4 i2_2_lut_3_lut (.A(cnt_1us[8]), .B(cnt_1us[5]), .C(n27383), .Z(n7)) /* synthesis lut_function=(((C)+!B)+!A) */ ;
    defparam i2_2_lut_3_lut.init = 16'hf7f7;
    FD1S3DX cnt_1us_2272__i0 (.D(n107[0]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cnt_1us[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272__i0.GSR = "DISABLED";
    LUT4 i4_4_lut_adj_258 (.A(cnt_1us[15]), .B(cnt_1us[13]), .C(cnt_1us[17]), 
         .D(n6_adj_1786), .Z(n15713)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(211[28:46])
    defparam i4_4_lut_adj_258.init = 16'hfffe;
    LUT4 i1_2_lut (.A(cnt_1us[16]), .B(cnt_1us[18]), .Z(n6_adj_1786)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(211[28:46])
    defparam i1_2_lut.init = 16'heeee;
    LUT4 i4_4_lut_adj_259 (.A(cnt_1us[11]), .B(cnt_1us[14]), .C(cnt_1us[10]), 
         .D(n6_adj_1787), .Z(n15754)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(241[37:53])
    defparam i4_4_lut_adj_259.init = 16'hfffe;
    CCU2D add_179_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(org_data[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .COUT(n24938), .S1(n642[0]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(327[18:40])
    defparam add_179_1.INIT0 = 16'hF000;
    defparam add_179_1.INIT1 = 16'haaaa;
    defparam add_179_1.INJECT1_0 = "NO";
    defparam add_179_1.INJECT1_1 = "NO";
    LUT4 i1_2_lut_adj_260 (.A(cnt_1us[12]), .B(cnt_1us[9]), .Z(n6_adj_1787)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(241[37:53])
    defparam i1_2_lut_adj_260.init = 16'heeee;
    CCU2D add_179_11 (.A0(org_data[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(org_data[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n24942), .S0(n642[9]), .S1(n642[10]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(327[18:40])
    defparam add_179_11.INIT0 = 16'ha555;
    defparam add_179_11.INIT1 = 16'ha555;
    defparam add_179_11.INJECT1_0 = "NO";
    defparam add_179_11.INJECT1_1 = "NO";
    LUT4 i2139_3_lut (.A(n29644), .B(wr_cnt[3]), .C(n21329), .Z(n7577)) /* synthesis lut_function=(A (B)+!A (B+!(C))) */ ;
    defparam i2139_3_lut.init = 16'hcdcd;
    FD1P3DX i171_205 (.D(dq_N_811), .SP(dq_N_800), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(dq_N_757)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam i171_205.GSR = "DISABLED";
    LUT4 i1_2_lut_4_lut (.A(n29586), .B(n29585), .C(n2113), .D(n2128), 
         .Z(n15859)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_2_lut_4_lut.init = 16'hfffe;
    LUT4 i1_2_lut_rep_420 (.A(flow_cnt[1]), .B(flow_cnt[0]), .Z(n29696)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(210[21:25])
    defparam i1_2_lut_rep_420.init = 16'heeee;
    LUT4 i14648_2_lut (.A(cnt_1us[4]), .B(cnt_1us[5]), .Z(n20687)) /* synthesis lut_function=(A (B)) */ ;
    defparam i14648_2_lut.init = 16'h8888;
    LUT4 i1_4_lut_adj_261 (.A(n399[5]), .B(org_data[5]), .C(n2131), .D(n15859), 
         .Z(org_data_15__N_714[5])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_261.init = 16'heca0;
    LUT4 i3002_2_lut_3_lut_4_lut_then_4_lut (.A(cmd_cnt[2]), .B(cmd_cnt[1]), 
         .C(cmd_cnt[0]), .D(cmd_cnt[3]), .Z(n30948)) /* synthesis lut_function=(!(A (B (C)+!B !(C+(D)))+!A !(B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(254[22] 259[20])
    defparam i3002_2_lut_3_lut_4_lut_then_4_lut.init = 16'h6a68;
    LUT4 i22155_3_lut_rep_366_4_lut (.A(flow_cnt[1]), .B(flow_cnt[0]), .C(flow_cnt[3]), 
         .D(flow_cnt[2]), .Z(n29642)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(210[21:25])
    defparam i22155_3_lut_rep_366_4_lut.init = 16'h0100;
    FD1S3DX temp_data_i11 (.D(data1[10]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(\temp_data[10] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(344[9:28])
    defparam temp_data_i11.GSR = "DISABLED";
    LUT4 i1_2_lut_3_lut (.A(flow_cnt[1]), .B(flow_cnt[0]), .C(flow_cnt[2]), 
         .Z(n4_adj_1788)) /* synthesis lut_function=(!(A (C)+!A ((C)+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(210[21:25])
    defparam i1_2_lut_3_lut.init = 16'h0e0e;
    LUT4 i2_3_lut (.A(cnt_1us[2]), .B(n15713), .C(n15760), .Z(n27699)) /* synthesis lut_function=((B+(C))+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(210[21:25])
    defparam i2_3_lut.init = 16'hfdfd;
    LUT4 i3165_3_lut_rep_274_4_lut_4_lut (.A(flow_cnt[1]), .B(n30946), .C(flow_cnt[0]), 
         .D(n21294), .Z(n29550)) /* synthesis lut_function=(A (B+(C+(D)))+!A (B)) */ ;
    defparam i3165_3_lut_rep_274_4_lut_4_lut.init = 16'heeec;
    LUT4 i3_4_lut_adj_262 (.A(cnt_1us[6]), .B(n20687), .C(cnt_1us[8]), 
         .D(cnt_1us[7]), .Z(n21264)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i3_4_lut_adj_262.init = 16'h8000;
    LUT4 i2_3_lut_adj_263 (.A(n27735), .B(cnt_1us[19]), .C(n15754), .Z(n15760)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(293[33:50])
    defparam i2_3_lut_adj_263.init = 16'hfefe;
    LUT4 mux_113_i2_4_lut_then_2_lut (.A(flow_cnt[1]), .B(n21375), .Z(n29714)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(304[22] 308[20])
    defparam mux_113_i2_4_lut_then_2_lut.init = 16'h2222;
    CCU2D add_179_9 (.A0(org_data[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(org_data[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n24941), .COUT(n24942), .S0(n642[7]), .S1(n642[8]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(327[18:40])
    defparam add_179_9.INIT0 = 16'ha555;
    defparam add_179_9.INIT1 = 16'ha555;
    defparam add_179_9.INJECT1_0 = "NO";
    defparam add_179_9.INJECT1_1 = "NO";
    LUT4 i2_3_lut_adj_264 (.A(cnt_1us[1]), .B(cnt_1us[3]), .C(cnt_1us[0]), 
         .Z(n27735)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(293[33:50])
    defparam i2_3_lut_adj_264.init = 16'hfefe;
    LUT4 i2_4_lut (.A(n29698), .B(n27736), .C(n29579), .D(cnt_1us[6]), 
         .Z(n21294)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(241[37:53])
    defparam i2_4_lut.init = 16'hfefa;
    LUT4 i2053_2_lut_2_lut_4_lut_2_lut_4_lut (.A(flow_cnt[2]), .B(flow_cnt[3]), 
         .Z(n7488)) /* synthesis lut_function=(!(A+(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(292[25:29])
    defparam i2053_2_lut_2_lut_4_lut_2_lut_4_lut.init = 16'h1111;
    LUT4 i3_4_lut_adj_265 (.A(cnt_1us[5]), .B(cnt_1us[4]), .C(cnt_1us[2]), 
         .D(n27735), .Z(n27736)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(293[33:50])
    defparam i3_4_lut_adj_265.init = 16'hfffe;
    LUT4 i22260_3_lut_2_lut_3_lut_4_lut (.A(flow_cnt[2]), .B(flow_cnt[3]), 
         .C(flow_cnt[1]), .D(flow_cnt[0]), .Z(n28080)) /* synthesis lut_function=(A+(B+!(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(292[25:29])
    defparam i22260_3_lut_2_lut_3_lut_4_lut.init = 16'heeef;
    LUT4 i2_3_lut_adj_266 (.A(cnt_1us[6]), .B(cnt_1us[7]), .C(cnt_1us[4]), 
         .Z(n27383)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(241[37:53])
    defparam i2_3_lut_adj_266.init = 16'hfefe;
    LUT4 n21329_bdd_3_lut_22839 (.A(n29618), .B(flow_cnt[2]), .C(wr_cnt[3]), 
         .Z(n29716)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam n21329_bdd_3_lut_22839.init = 16'h8080;
    LUT4 i2_2_lut_rep_344_3_lut_4_lut (.A(flow_cnt[2]), .B(flow_cnt[3]), 
         .C(flow_cnt[1]), .D(flow_cnt[0]), .Z(n29620)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(292[25:29])
    defparam i2_2_lut_rep_344_3_lut_4_lut.init = 16'h1000;
    LUT4 i3164_3_lut_rep_276_4_lut_4_lut (.A(flow_cnt[1]), .B(n30946), .C(flow_cnt[0]), 
         .D(n21329), .Z(n29552)) /* synthesis lut_function=(A (B+(C+!(D)))+!A (B)) */ ;
    defparam i3164_3_lut_rep_276_4_lut_4_lut.init = 16'hecee;
    LUT4 n1676_bdd_2_lut_22409 (.A(n28798), .B(n2110), .Z(n28799)) /* synthesis lut_function=(A (B)) */ ;
    defparam n1676_bdd_2_lut_22409.init = 16'h8888;
    LUT4 i15067_2_lut_rep_273_4_lut (.A(flow_cnt[1]), .B(n30946), .C(flow_cnt[0]), 
         .D(n21294), .Z(n29549)) /* synthesis lut_function=((B+(C+!(D)))+!A) */ ;
    defparam i15067_2_lut_rep_273_4_lut.init = 16'hfdff;
    LUT4 wr_cnt_2__I_0_i5_3_lut (.A(wr_data[6]), .B(wr_data[7]), .C(wr_cnt[0]), 
         .Z(n5_adj_1789)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(240[51:57])
    defparam wr_cnt_2__I_0_i5_3_lut.init = 16'hcaca;
    LUT4 n2110_bdd_4_lut_22541 (.A(n7488), .B(flow_cnt[0]), .C(flow_cnt[1]), 
         .D(n29556), .Z(n28798)) /* synthesis lut_function=((B (C+!(D))+!B !(C))+!A) */ ;
    defparam n2110_bdd_4_lut_22541.init = 16'hd7df;
    LUT4 i2_3_lut_rep_368_4_lut (.A(flow_cnt[2]), .B(flow_cnt[3]), .C(flow_cnt[0]), 
         .D(flow_cnt[1]), .Z(n29644)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(292[25:29])
    defparam i2_3_lut_rep_368_4_lut.init = 16'hfeff;
    LUT4 wr_cnt_2__I_0_i4_3_lut (.A(wr_data[4]), .B(wr_data[5]), .C(wr_cnt[0]), 
         .Z(n4_adj_1790)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(240[51:57])
    defparam wr_cnt_2__I_0_i4_3_lut.init = 16'hcaca;
    LUT4 i2_3_lut_4_lut_adj_267 (.A(cnt_1us[1]), .B(n29700), .C(cnt_1us[0]), 
         .D(n20687), .Z(n21242)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i2_3_lut_4_lut_adj_267.init = 16'h8000;
    LUT4 equal_1446_i5_2_lut_rep_367_3_lut (.A(flow_cnt[2]), .B(flow_cnt[3]), 
         .C(flow_cnt[1]), .Z(n29643)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(292[25:29])
    defparam equal_1446_i5_2_lut_rep_367_3_lut.init = 16'hfefe;
    LUT4 i10381_3_lut_4_lut (.A(flow_cnt[0]), .B(n39), .C(n29643), .D(n21375), 
         .Z(n16451)) /* synthesis lut_function=(!(A (B (C (D))+!B (D))+!A (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam i10381_3_lut_4_lut.init = 16'h08ff;
    LUT4 wr_cnt_2__I_0_i2_3_lut (.A(wr_data[2]), .B(wr_data[3]), .C(wr_cnt[0]), 
         .Z(n2_adj_1791)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(240[51:57])
    defparam wr_cnt_2__I_0_i2_3_lut.init = 16'hcaca;
    LUT4 i1_2_lut_rep_422 (.A(cnt_1us[7]), .B(cnt_1us[8]), .Z(n29698)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(241[37:53])
    defparam i1_2_lut_rep_422.init = 16'heeee;
    LUT4 i1_2_lut_3_lut_adj_268 (.A(cnt_1us[7]), .B(cnt_1us[8]), .C(cnt_1us[6]), 
         .Z(n15774)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(241[37:53])
    defparam i1_2_lut_3_lut_adj_268.init = 16'hfefe;
    LUT4 i14380_2_lut (.A(n85[1]), .B(cnt_1us_en), .Z(n107[1])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i14380_2_lut.init = 16'h8888;
    FD1S3DX temp_data_i10 (.D(data1[9]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(\temp_data[9] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(344[9:28])
    defparam temp_data_i10.GSR = "DISABLED";
    FD1S3DX temp_data_i9 (.D(data1[8]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(\temp_data[8] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(344[9:28])
    defparam temp_data_i9.GSR = "DISABLED";
    FD1S3DX temp_data_i8 (.D(data1[7]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(\temp_data[7] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(344[9:28])
    defparam temp_data_i8.GSR = "DISABLED";
    FD1S3DX temp_data_i7 (.D(data1[6]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(\temp_data[6] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(344[9:28])
    defparam temp_data_i7.GSR = "DISABLED";
    FD1S3DX temp_data_i6 (.D(data1[5]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(\temp_data[5] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(344[9:28])
    defparam temp_data_i6.GSR = "DISABLED";
    FD1S3DX temp_data_i5 (.D(data1[4]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(\temp_data[4] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(344[9:28])
    defparam temp_data_i5.GSR = "DISABLED";
    FD1S3DX temp_data_i4 (.D(data1[3]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(\temp_data[3] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(344[9:28])
    defparam temp_data_i4.GSR = "DISABLED";
    FD1S3DX temp_data_i3 (.D(data1[2]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(\temp_data[2] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(344[9:28])
    defparam temp_data_i3.GSR = "DISABLED";
    FD1S3DX temp_data_i2 (.D(data1[1]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(\temp_data[1] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(344[9:28])
    defparam temp_data_i2.GSR = "DISABLED";
    FD1S3DX data1_i10 (.D(data1_10__N_635[10]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(data1[10])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(321[10] 328[8])
    defparam data1_i10.GSR = "DISABLED";
    FD1S3DX data1_i9 (.D(data1_10__N_635[9]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(data1[9])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(321[10] 328[8])
    defparam data1_i9.GSR = "DISABLED";
    FD1S3DX data1_i8 (.D(data1_10__N_635[8]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(data1[8])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(321[10] 328[8])
    defparam data1_i8.GSR = "DISABLED";
    FD1S3DX data1_i7 (.D(data1_10__N_635[7]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(data1[7])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(321[10] 328[8])
    defparam data1_i7.GSR = "DISABLED";
    FD1S3DX data1_i6 (.D(data1_10__N_635[6]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(data1[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(321[10] 328[8])
    defparam data1_i6.GSR = "DISABLED";
    FD1S3DX data1_i5 (.D(data1_10__N_635[5]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(data1[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(321[10] 328[8])
    defparam data1_i5.GSR = "DISABLED";
    FD1S3DX data1_i4 (.D(data1_10__N_635[4]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(data1[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(321[10] 328[8])
    defparam data1_i4.GSR = "DISABLED";
    FD1S3DX data1_i3 (.D(data1_10__N_635[3]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(data1[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(321[10] 328[8])
    defparam data1_i3.GSR = "DISABLED";
    FD1S3DX data1_i2 (.D(data1_10__N_635[2]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(data1[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(321[10] 328[8])
    defparam data1_i2.GSR = "DISABLED";
    FD1S3DX data1_i1 (.D(data1_10__N_635[1]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(data1[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(321[10] 328[8])
    defparam data1_i1.GSR = "DISABLED";
    FD1S3DX cmd_cnt_i3 (.D(cmd_cnt_3__N_646[3]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cmd_cnt[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam cmd_cnt_i3.GSR = "DISABLED";
    FD1S3DX cmd_cnt_i2 (.D(cmd_cnt_3__N_646[2]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cmd_cnt[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam cmd_cnt_i2.GSR = "DISABLED";
    FD1S3DX cmd_cnt_i1 (.D(cmd_cnt_3__N_646[1]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cmd_cnt[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam cmd_cnt_i1.GSR = "DISABLED";
    FD1S3DX wr_cnt_i3 (.D(wr_cnt_3__N_581[3]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(wr_cnt[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam wr_cnt_i3.GSR = "DISABLED";
    FD1S3DX wr_cnt_i2 (.D(wr_cnt_3__N_581[2]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(wr_cnt[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam wr_cnt_i2.GSR = "DISABLED";
    FD1S3DX wr_cnt_i1 (.D(wr_cnt_3__N_581[1]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(wr_cnt[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam wr_cnt_i1.GSR = "DISABLED";
    FD1S3DX rd_cnt_i4 (.D(rd_cnt_4__N_585[4]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(rd_cnt[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam rd_cnt_i4.GSR = "DISABLED";
    FD1S3DX rd_cnt_i3 (.D(rd_cnt_4__N_585[3]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(rd_cnt[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam rd_cnt_i3.GSR = "DISABLED";
    FD1S3DX rd_cnt_i2 (.D(rd_cnt_4__N_585[2]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(rd_cnt[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam rd_cnt_i2.GSR = "DISABLED";
    FD1S3DX rd_cnt_i1 (.D(rd_cnt_4__N_585[1]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(rd_cnt[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam rd_cnt_i1.GSR = "DISABLED";
    FD1S3DX rd_data_i15 (.D(rd_data_15__N_603[15]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(rd_data[15])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam rd_data_i15.GSR = "DISABLED";
    FD1S3DX rd_data_i14 (.D(rd_data_15__N_603[14]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(rd_data[14])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam rd_data_i14.GSR = "DISABLED";
    FD1S3DX rd_data_i13 (.D(rd_data_15__N_603[13]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(rd_data[13])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam rd_data_i13.GSR = "DISABLED";
    FD1S3DX rd_data_i12 (.D(rd_data_15__N_603[12]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(rd_data[12])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam rd_data_i12.GSR = "DISABLED";
    FD1S3DX rd_data_i11 (.D(rd_data_15__N_603[11]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(rd_data[11])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam rd_data_i11.GSR = "DISABLED";
    FD1S3DX rd_data_i10 (.D(rd_data_15__N_603[10]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(rd_data[10])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam rd_data_i10.GSR = "DISABLED";
    FD1S3DX rd_data_i9 (.D(rd_data_15__N_603[9]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(rd_data[9])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam rd_data_i9.GSR = "DISABLED";
    FD1S3DX rd_data_i8 (.D(rd_data_15__N_603[8]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(rd_data[8])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam rd_data_i8.GSR = "DISABLED";
    FD1S3DX rd_data_i7 (.D(rd_data_15__N_603[7]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(rd_data[7])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam rd_data_i7.GSR = "DISABLED";
    FD1S3DX rd_data_i6 (.D(rd_data_15__N_603[6]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(rd_data[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam rd_data_i6.GSR = "DISABLED";
    FD1S3DX rd_data_i5 (.D(rd_data_15__N_603[5]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(rd_data[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam rd_data_i5.GSR = "DISABLED";
    FD1S3DX rd_data_i4 (.D(rd_data_15__N_603[4]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(rd_data[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam rd_data_i4.GSR = "DISABLED";
    FD1S3DX rd_data_i3 (.D(rd_data_15__N_603[3]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(rd_data[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam rd_data_i3.GSR = "DISABLED";
    FD1S3DX rd_data_i2 (.D(rd_data_15__N_603[2]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(rd_data[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam rd_data_i2.GSR = "DISABLED";
    FD1S3DX rd_data_i1 (.D(rd_data_15__N_603[1]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(rd_data[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam rd_data_i1.GSR = "DISABLED";
    LUT4 i14755_2_lut (.A(n85[2]), .B(cnt_1us_en), .Z(n107[2])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i14755_2_lut.init = 16'h8888;
    FD1P3AX wr_data_i0_i7 (.D(wr_data_7__N_730[7]), .SP(DS18B20_rst), .CK(clk_1us), 
            .Q(wr_data[7])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam wr_data_i0_i7.GSR = "DISABLED";
    LUT4 i14756_2_lut (.A(n85[3]), .B(cnt_1us_en), .Z(n107[3])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i14756_2_lut.init = 16'h8888;
    FD1P3AX wr_data_i0_i6 (.D(wr_data_7__N_730[6]), .SP(DS18B20_rst), .CK(clk_1us), 
            .Q(wr_data[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam wr_data_i0_i6.GSR = "DISABLED";
    LUT4 i14757_2_lut (.A(n85[4]), .B(cnt_1us_en), .Z(n107[4])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i14757_2_lut.init = 16'h8888;
    FD1P3AX wr_data_i0_i3 (.D(wr_data_7__N_730[3]), .SP(DS18B20_rst), .CK(clk_1us), 
            .Q(wr_data[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam wr_data_i0_i3.GSR = "DISABLED";
    FD1P3AX wr_data_i0_i2 (.D(wr_data_7__N_730[2]), .SP(DS18B20_rst), .CK(clk_1us), 
            .Q(wr_data[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam wr_data_i0_i2.GSR = "DISABLED";
    FD1S3DX flow_cnt_i3 (.D(flow_cnt_3__N_577[3]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(flow_cnt[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam flow_cnt_i3.GSR = "DISABLED";
    FD1S3DX flow_cnt_i2 (.D(flow_cnt_3__N_577[2]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(flow_cnt[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam flow_cnt_i2.GSR = "DISABLED";
    FD1S3DX flow_cnt_i1 (.D(flow_cnt_3__N_577[1]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(flow_cnt[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam flow_cnt_i1.GSR = "DISABLED";
    FD1P3AX org_data_i0_i15 (.D(org_data_15__N_714[15]), .SP(DS18B20_rst), 
            .CK(clk_1us), .Q(n33[15])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam org_data_i0_i15.GSR = "DISABLED";
    LUT4 i14758_2_lut (.A(n85[5]), .B(cnt_1us_en), .Z(n107[5])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i14758_2_lut.init = 16'h8888;
    FD1P3AX org_data_i0_i10 (.D(org_data_15__N_714[10]), .SP(DS18B20_rst), 
            .CK(clk_1us), .Q(org_data[10])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam org_data_i0_i10.GSR = "DISABLED";
    FD1P3AX org_data_i0_i9 (.D(org_data_15__N_714[9]), .SP(DS18B20_rst), 
            .CK(clk_1us), .Q(org_data[9])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam org_data_i0_i9.GSR = "DISABLED";
    FD1P3AX org_data_i0_i8 (.D(org_data_15__N_714[8]), .SP(DS18B20_rst), 
            .CK(clk_1us), .Q(org_data[8])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam org_data_i0_i8.GSR = "DISABLED";
    FD1P3AX org_data_i0_i7 (.D(org_data_15__N_714[7]), .SP(DS18B20_rst), 
            .CK(clk_1us), .Q(org_data[7])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam org_data_i0_i7.GSR = "DISABLED";
    FD1P3AX org_data_i0_i6 (.D(org_data_15__N_714[6]), .SP(DS18B20_rst), 
            .CK(clk_1us), .Q(org_data[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam org_data_i0_i6.GSR = "DISABLED";
    FD1P3AX org_data_i0_i5 (.D(org_data_15__N_714[5]), .SP(DS18B20_rst), 
            .CK(clk_1us), .Q(org_data[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam org_data_i0_i5.GSR = "DISABLED";
    FD1P3AX org_data_i0_i4 (.D(org_data_15__N_714[4]), .SP(DS18B20_rst), 
            .CK(clk_1us), .Q(org_data[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam org_data_i0_i4.GSR = "DISABLED";
    FD1P3AX org_data_i0_i3 (.D(org_data_15__N_714[3]), .SP(DS18B20_rst), 
            .CK(clk_1us), .Q(org_data[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam org_data_i0_i3.GSR = "DISABLED";
    FD1P3AX org_data_i0_i2 (.D(org_data_15__N_714[2]), .SP(DS18B20_rst), 
            .CK(clk_1us), .Q(org_data[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam org_data_i0_i2.GSR = "DISABLED";
    FD1P3AX org_data_i0_i1 (.D(org_data_15__N_714[1]), .SP(DS18B20_rst), 
            .CK(clk_1us), .Q(org_data[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam org_data_i0_i1.GSR = "DISABLED";
    LUT4 i14759_2_lut (.A(n85[6]), .B(cnt_1us_en), .Z(n107[6])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i14759_2_lut.init = 16'h8888;
    LUT4 i1_2_lut_rep_424 (.A(cnt_1us[2]), .B(cnt_1us[3]), .Z(n29700)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_rep_424.init = 16'h8888;
    LUT4 i1_2_lut_rep_369_3_lut (.A(cnt_1us[2]), .B(cnt_1us[3]), .C(cnt_1us[1]), 
         .Z(n29645)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i1_2_lut_rep_369_3_lut.init = 16'h8080;
    LUT4 i1_3_lut_4_lut_adj_269 (.A(cnt_1us[2]), .B(cnt_1us[3]), .C(n27765), 
         .D(n21242), .Z(n21329)) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (C)) */ ;
    defparam i1_3_lut_4_lut_adj_269.init = 16'hf8f0;
    FD1S3DX cur_state_FSM_i2 (.D(n2113), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(n2095[2]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam cur_state_FSM_i2.GSR = "DISABLED";
    LUT4 i1_4_lut_adj_270 (.A(rd_data_15__N_685[0]), .B(rd_data[0]), .C(n2131), 
         .D(n15859), .Z(rd_data_15__N_603[0])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_270.init = 16'heca0;
    LUT4 i14760_2_lut (.A(n85[7]), .B(cnt_1us_en), .Z(n107[7])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i14760_2_lut.init = 16'h8888;
    FD1P3DX cur_state_FSM_i3 (.D(n15071), .SP(next_state_2__N_565[1]), .CK(clk_1us), 
            .CD(rst_n_N_535), .Q(n2095[3]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam cur_state_FSM_i3.GSR = "DISABLED";
    FD1S3DX cur_state_FSM_i4 (.D(n2122), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(n2095[4]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam cur_state_FSM_i4.GSR = "DISABLED";
    FD1S3DX cur_state_FSM_i5 (.D(n2125), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(n2095[5]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam cur_state_FSM_i5.GSR = "DISABLED";
    FD1S3DX cur_state_FSM_i6 (.D(n2128), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(n2095[6]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam cur_state_FSM_i6.GSR = "DISABLED";
    FD1S3DX cur_state_FSM_i7 (.D(n2131), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(n2095[7]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam cur_state_FSM_i7.GSR = "DISABLED";
    LUT4 i14761_2_lut (.A(n85[8]), .B(cnt_1us_en), .Z(n107[8])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i14761_2_lut.init = 16'h8888;
    LUT4 i14762_2_lut (.A(n85[9]), .B(cnt_1us_en), .Z(n107[9])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i14762_2_lut.init = 16'h8888;
    LUT4 i4618_3_lut (.A(rd_data[1]), .B(rd_data[0]), .C(n15156), .Z(rd_data_15__N_685[0])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i4618_3_lut.init = 16'hcaca;
    LUT4 i14763_2_lut (.A(n85[10]), .B(cnt_1us_en), .Z(n107[10])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i14763_2_lut.init = 16'h8888;
    LUT4 i14764_2_lut (.A(n85[11]), .B(cnt_1us_en), .Z(n107[11])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i14764_2_lut.init = 16'h8888;
    LUT4 i14765_2_lut (.A(n85[12]), .B(cnt_1us_en), .Z(n107[12])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i14765_2_lut.init = 16'h8888;
    LUT4 i14766_2_lut (.A(n85[13]), .B(cnt_1us_en), .Z(n107[13])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i14766_2_lut.init = 16'h8888;
    LUT4 i14767_2_lut (.A(n85[14]), .B(cnt_1us_en), .Z(n107[14])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i14767_2_lut.init = 16'h8888;
    LUT4 i14768_2_lut (.A(n85[15]), .B(cnt_1us_en), .Z(n107[15])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i14768_2_lut.init = 16'h8888;
    LUT4 i3_4_lut_adj_271 (.A(n29643), .B(n29659), .C(n29541), .D(n29644), 
         .Z(n15156)) /* synthesis lut_function=(A+((C+!(D))+!B)) */ ;
    defparam i3_4_lut_adj_271.init = 16'hfbff;
    LUT4 i14769_2_lut (.A(n85[16]), .B(cnt_1us_en), .Z(n107[16])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i14769_2_lut.init = 16'h8888;
    LUT4 i14770_2_lut (.A(n85[17]), .B(cnt_1us_en), .Z(n107[17])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i14770_2_lut.init = 16'h8888;
    LUT4 i14771_2_lut (.A(n85[18]), .B(cnt_1us_en), .Z(n107[18])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i14771_2_lut.init = 16'h8888;
    LUT4 i1_4_lut_adj_272 (.A(n25525), .B(next_state_2__N_574[1]), .C(n29618), 
         .D(n29578), .Z(init_done_N_760)) /* synthesis lut_function=(A+(B (C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_272.init = 16'heeea;
    LUT4 i14772_2_lut (.A(n85[19]), .B(cnt_1us_en), .Z(n107[19])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i14772_2_lut.init = 16'h8888;
    LUT4 i2_3_lut_adj_273 (.A(n29642), .B(n39_adj_1785), .C(n2110), .Z(n25525)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;
    defparam i2_3_lut_adj_273.init = 16'h2020;
    LUT4 i2_4_lut_adj_274 (.A(n27699), .B(n29693), .C(cnt_1us[4]), .D(n27965), 
         .Z(n39_adj_1785)) /* synthesis lut_function=(A+!(B (C (D)))) */ ;
    defparam i2_4_lut_adj_274.init = 16'hbfff;
    LUT4 i21817_2_lut (.A(cnt_1us[6]), .B(cnt_1us[7]), .Z(n27965)) /* synthesis lut_function=(A (B)) */ ;
    defparam i21817_2_lut.init = 16'h8888;
    FD1S3DX cnt_1us_2272__i1 (.D(n107[1]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cnt_1us[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272__i1.GSR = "DISABLED";
    FD1S3DX cnt_1us_2272__i2 (.D(n107[2]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cnt_1us[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272__i2.GSR = "DISABLED";
    FD1S3DX cnt_1us_2272__i3 (.D(n107[3]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cnt_1us[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272__i3.GSR = "DISABLED";
    FD1S3DX cnt_1us_2272__i4 (.D(n107[4]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cnt_1us[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272__i4.GSR = "DISABLED";
    FD1S3DX cnt_1us_2272__i5 (.D(n107[5]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cnt_1us[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272__i5.GSR = "DISABLED";
    FD1S3DX cnt_1us_2272__i6 (.D(n107[6]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cnt_1us[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272__i6.GSR = "DISABLED";
    FD1S3DX cnt_1us_2272__i7 (.D(n107[7]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cnt_1us[7])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272__i7.GSR = "DISABLED";
    FD1S3DX cnt_1us_2272__i8 (.D(n107[8]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cnt_1us[8])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272__i8.GSR = "DISABLED";
    FD1S3DX cnt_1us_2272__i9 (.D(n107[9]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cnt_1us[9])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272__i9.GSR = "DISABLED";
    FD1S3DX cnt_1us_2272__i10 (.D(n107[10]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cnt_1us[10])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272__i10.GSR = "DISABLED";
    FD1S3DX cnt_1us_2272__i11 (.D(n107[11]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cnt_1us[11])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272__i11.GSR = "DISABLED";
    FD1S3DX cnt_1us_2272__i12 (.D(n107[12]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cnt_1us[12])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272__i12.GSR = "DISABLED";
    FD1S3DX cnt_1us_2272__i13 (.D(n107[13]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cnt_1us[13])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272__i13.GSR = "DISABLED";
    FD1S3DX cnt_1us_2272__i14 (.D(n107[14]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cnt_1us[14])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272__i14.GSR = "DISABLED";
    FD1S3DX cnt_1us_2272__i15 (.D(n107[15]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cnt_1us[15])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272__i15.GSR = "DISABLED";
    FD1S3DX cnt_1us_2272__i16 (.D(n107[16]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cnt_1us[16])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272__i16.GSR = "DISABLED";
    FD1S3DX cnt_1us_2272__i17 (.D(n107[17]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cnt_1us[17])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272__i17.GSR = "DISABLED";
    FD1S3DX cnt_1us_2272__i18 (.D(n107[18]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cnt_1us[18])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272__i18.GSR = "DISABLED";
    FD1S3DX cnt_1us_2272__i19 (.D(n107[19]), .CK(clk_1us), .CD(rst_n_N_535), 
            .Q(cnt_1us[19])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272__i19.GSR = "DISABLED";
    LUT4 wr_cnt_3__bdd_4_lut_23413 (.A(wr_cnt[3]), .B(cmd_cnt[1]), .C(cmd_cnt[2]), 
         .D(cmd_cnt[0]), .Z(n30933)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam wr_cnt_3__bdd_4_lut_23413.init = 16'h8000;
    LUT4 i4_4_lut_adj_275 (.A(n26651), .B(n8), .C(cnt_1us_en_N_787), .D(n2110), 
         .Z(cnt_1us_en_N_770)) /* synthesis lut_function=(A+(B+(C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i4_4_lut_adj_275.init = 16'hfeee;
    LUT4 i1_4_lut_adj_276 (.A(n2131), .B(n27529), .C(cnt_1us_en), .D(n9), 
         .Z(n26651)) /* synthesis lut_function=(A (B+(C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_276.init = 16'ha888;
    LUT4 i3_4_lut_adj_277 (.A(n5_adj_1792), .B(n3_adj_1793), .C(cnt_1us_en), 
         .D(n29577), .Z(n8)) /* synthesis lut_function=(A+(B+(C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i3_4_lut_adj_277.init = 16'hfeee;
    LUT4 i10567_2_lut (.A(DS18B20_rst), .B(n2128), .Z(n16641)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam i10567_2_lut.init = 16'h8888;
    LUT4 i1_4_lut_adj_278 (.A(n29644), .B(n29659), .C(flow_cnt[0]), .D(n29643), 
         .Z(n27529)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_278.init = 16'h0008;
    LUT4 select_561_Select_0_i5_2_lut (.A(st_done_N_781), .B(n2125), .Z(n5_adj_1792)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam select_561_Select_0_i5_2_lut.init = 16'h8888;
    LUT4 select_561_Select_0_i3_4_lut (.A(n5016[0]), .B(n29618), .C(cnt_1us_en), 
         .D(n25277), .Z(n3_adj_1793)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam select_561_Select_0_i3_4_lut.init = 16'hc088;
    LUT4 i14773_3_lut (.A(cnt_1us_en), .B(flow_cnt[1]), .C(flow_cnt[0]), 
         .Z(n5016[0])) /* synthesis lut_function=(!(A (B)+!A (B+(C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(229[21] 252[28])
    defparam i14773_3_lut.init = 16'h2323;
    LUT4 i2_4_lut_adj_279 (.A(wr_cnt[3]), .B(flow_cnt[0]), .C(n30946), 
         .D(flow_cnt[1]), .Z(n25277)) /* synthesis lut_function=(A+(B (C)+!B (C+(D)))) */ ;
    defparam i2_4_lut_adj_279.init = 16'hfbfa;
    LUT4 i4_4_lut_adj_280 (.A(n7), .B(n28024), .C(cnt_1us[2]), .D(n15760), 
         .Z(st_done_N_781)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ;
    defparam i4_4_lut_adj_280.init = 16'hfffb;
    LUT4 i2788_2_lut_rep_381 (.A(flow_cnt[1]), .B(flow_cnt[0]), .Z(n29657)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(283[41:56])
    defparam i2788_2_lut_rep_381.init = 16'h6666;
    LUT4 i1_3_lut (.A(bit_width[4]), .B(n2131), .C(n29565), .Z(n15969)) /* synthesis lut_function=(A (B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_3_lut.init = 16'ha8a8;
    LUT4 i8291_4_lut_4_lut (.A(flow_cnt[1]), .B(flow_cnt[0]), .C(n29545), 
         .D(n13252), .Z(n7447)) /* synthesis lut_function=(A ((C+(D))+!B)+!A !((C+(D))+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(283[41:56])
    defparam i8291_4_lut_4_lut.init = 16'haaa6;
    LUT4 i21874_4_lut (.A(cnt_1us[13]), .B(cnt_1us[15]), .C(cnt_1us[16]), 
         .D(n27881), .Z(n28024)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i21874_4_lut.init = 16'h8000;
    LUT4 mux_113_i2_4_lut_else_2_lut (.A(flow_cnt[1]), .B(n21375), .C(n39), 
         .D(flow_cnt[0]), .Z(n29713)) /* synthesis lut_function=(A ((C+!(D))+!B)+!A !((C+!(D))+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(304[22] 308[20])
    defparam mux_113_i2_4_lut_else_2_lut.init = 16'ha6aa;
    LUT4 i21737_2_lut (.A(cnt_1us[17]), .B(cnt_1us[18]), .Z(n27881)) /* synthesis lut_function=(A (B)) */ ;
    defparam i21737_2_lut.init = 16'h8888;
    LUT4 dq_I_0_4_lut (.A(DS18B20_bus_out), .B(n29644), .C(dq_N_800), 
         .D(n4_adj_1794), .Z(dq_N_792)) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam dq_I_0_4_lut.init = 16'h3a0a;
    LUT4 i14711_2_lut_rep_383 (.A(bit_width[4]), .B(rd_cnt[4]), .Z(n29659)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(278[20:38])
    defparam i14711_2_lut_rep_383.init = 16'h2222;
    LUT4 mux_117_i1_3_lut_4_lut (.A(bit_width[4]), .B(rd_cnt[4]), .C(org_data[0]), 
         .D(rd_data[0]), .Z(n399[0])) /* synthesis lut_function=(A (B (D)+!B (C))+!A (D)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(278[20:38])
    defparam mux_117_i1_3_lut_4_lut.init = 16'hfd20;
    LUT4 i1_2_lut_3_lut_adj_281 (.A(bit_width[4]), .B(rd_cnt[4]), .C(n2131), 
         .Z(n27530)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(278[20:38])
    defparam i1_2_lut_3_lut_adj_281.init = 16'h2020;
    LUT4 i1_3_lut_4_lut_adj_282 (.A(n15713), .B(n15754), .C(n15774), .D(cnt_1us[19]), 
         .Z(n27765)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(241[37:53])
    defparam i1_3_lut_4_lut_adj_282.init = 16'hfffe;
    LUT4 i2_4_lut_adj_283 (.A(n27531), .B(n27606), .C(n7488), .D(n4_adj_1795), 
         .Z(dq_N_800)) /* synthesis lut_function=(A+(B+(C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i2_4_lut_adj_283.init = 16'hfeee;
    LUT4 mux_117_i10_3_lut_4_lut (.A(bit_width[4]), .B(rd_cnt[4]), .C(org_data[9]), 
         .D(rd_data[9]), .Z(n399[9])) /* synthesis lut_function=(A (B (D)+!B (C))+!A (D)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(278[20:38])
    defparam mux_117_i10_3_lut_4_lut.init = 16'hfd20;
    LUT4 i1_4_lut_adj_284 (.A(n21294), .B(n27530), .C(n21210), .D(flow_cnt[1]), 
         .Z(n27531)) /* synthesis lut_function=(!(A ((C+(D))+!B)+!A ((C)+!B))) */ ;
    defparam i1_4_lut_adj_284.init = 16'h040c;
    FD1P3JX wr_data_i0_i1 (.D(n15958), .SP(DS18B20_rst), .PD(n16641), 
            .CK(clk_1us), .Q(wr_data[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam wr_data_i0_i1.GSR = "DISABLED";
    LUT4 i1_4_lut_adj_285 (.A(flow_cnt[0]), .B(n2110), .C(dq_N_809), .D(flow_cnt[1]), 
         .Z(n4_adj_1795)) /* synthesis lut_function=(!(A ((D)+!B)+!A !(B (C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_285.init = 16'h4088;
    LUT4 i2_4_lut_adj_286 (.A(flow_cnt[3]), .B(flow_cnt[0]), .C(flow_cnt[2]), 
         .D(flow_cnt[1]), .Z(n21210)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;
    defparam i2_4_lut_adj_286.init = 16'hfefa;
    LUT4 mux_117_i9_3_lut_4_lut (.A(bit_width[4]), .B(rd_cnt[4]), .C(org_data[8]), 
         .D(rd_data[8]), .Z(n399[8])) /* synthesis lut_function=(A (B (D)+!B (C))+!A (D)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(278[20:38])
    defparam mux_117_i9_3_lut_4_lut.init = 16'hfd20;
    LUT4 mux_117_i8_3_lut_4_lut (.A(bit_width[4]), .B(rd_cnt[4]), .C(org_data[7]), 
         .D(rd_data[7]), .Z(n399[7])) /* synthesis lut_function=(A (B (D)+!B (C))+!A (D)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(278[20:38])
    defparam mux_117_i8_3_lut_4_lut.init = 16'hfd20;
    LUT4 mux_1487_Mux_0_i3_4_lut (.A(flow_cnt[0]), .B(n27765), .C(flow_cnt[1]), 
         .D(n21242), .Z(n21345)) /* synthesis lut_function=(A+(B (C)+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(229[21] 252[28])
    defparam mux_1487_Mux_0_i3_4_lut.init = 16'hfaea;
    LUT4 mux_117_i7_3_lut_4_lut (.A(bit_width[4]), .B(rd_cnt[4]), .C(org_data[6]), 
         .D(rd_data[6]), .Z(n399[6])) /* synthesis lut_function=(A (B (D)+!B (C))+!A (D)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(278[20:38])
    defparam mux_117_i7_3_lut_4_lut.init = 16'hfd20;
    PFUMX i22022 (.BLUT(n1), .ALUT(n2_adj_1791), .C0(wr_cnt[1]), .Z(n28173));
    LUT4 mux_117_i6_3_lut_4_lut (.A(bit_width[4]), .B(rd_cnt[4]), .C(org_data[5]), 
         .D(rd_data[5]), .Z(n399[5])) /* synthesis lut_function=(A (B (D)+!B (C))+!A (D)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(278[20:38])
    defparam mux_117_i6_3_lut_4_lut.init = 16'hfd20;
    LUT4 mux_117_i5_3_lut_4_lut (.A(bit_width[4]), .B(rd_cnt[4]), .C(org_data[4]), 
         .D(rd_data[4]), .Z(n399[4])) /* synthesis lut_function=(A (B (D)+!B (C))+!A (D)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(278[20:38])
    defparam mux_117_i5_3_lut_4_lut.init = 16'hfd20;
    LUT4 mux_117_i4_3_lut_4_lut (.A(bit_width[4]), .B(rd_cnt[4]), .C(org_data[3]), 
         .D(rd_data[3]), .Z(n399[3])) /* synthesis lut_function=(A (B (D)+!B (C))+!A (D)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(278[20:38])
    defparam mux_117_i4_3_lut_4_lut.init = 16'hfd20;
    LUT4 mux_117_i3_3_lut_4_lut (.A(bit_width[4]), .B(rd_cnt[4]), .C(org_data[2]), 
         .D(rd_data[2]), .Z(n399[2])) /* synthesis lut_function=(A (B (D)+!B (C))+!A (D)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(278[20:38])
    defparam mux_117_i3_3_lut_4_lut.init = 16'hfd20;
    FD1P3JX wr_data_i0_i4 (.D(n15836), .SP(DS18B20_rst), .PD(n16641), 
            .CK(clk_1us), .Q(wr_data[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam wr_data_i0_i4.GSR = "DISABLED";
    LUT4 mux_117_i2_3_lut_4_lut (.A(bit_width[4]), .B(rd_cnt[4]), .C(org_data[1]), 
         .D(rd_data[1]), .Z(n399[1])) /* synthesis lut_function=(A (B (D)+!B (C))+!A (D)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(278[20:38])
    defparam mux_117_i2_3_lut_4_lut.init = 16'hfd20;
    LUT4 i22249_4_lut (.A(n29559), .B(n15774), .C(n29645), .D(cnt_1us[4]), 
         .Z(dq_N_809)) /* synthesis lut_function=(!(A+(B+(C (D))))) */ ;
    defparam i22249_4_lut.init = 16'h0111;
    LUT4 i1_4_lut_adj_287 (.A(n29577), .B(st_done_N_781), .C(n4_adj_1796), 
         .D(n2125), .Z(st_done_N_764)) /* synthesis lut_function=(A+(B (C)+!B (C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_287.init = 16'hfbfa;
    LUT4 i1_4_lut_adj_288 (.A(n29659), .B(wr_cnt[3]), .C(n2131), .D(n29618), 
         .Z(n4_adj_1796)) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_288.init = 16'hdc50;
    LUT4 i1_4_lut_adj_289 (.A(n29549), .B(n15859), .C(n27530), .D(rd_cnt[0]), 
         .Z(rd_cnt_4__N_585[0])) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (B (C+(D))+!B !((D)+!C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_289.init = 16'hec50;
    LUT4 i1_4_lut_adj_290 (.A(n5028[0]), .B(wr_cnt[0]), .C(n29602), .D(n29558), 
         .Z(wr_cnt_3__N_581[0])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_290.init = 16'heca0;
    LUT4 i3424_4_lut (.A(wr_cnt[0]), .B(flow_cnt[0]), .C(flow_cnt[1]), 
         .D(n30946), .Z(n5028[0])) /* synthesis lut_function=(A (((D)+!C)+!B)+!A !(((D)+!C)+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(229[21] 252[28])
    defparam i3424_4_lut.init = 16'haa6a;
    LUT4 i1_4_lut_adj_291 (.A(wr_cnt[3]), .B(n15812), .C(n29618), .D(n29600), 
         .Z(cmd_cnt_3__N_646[0])) /* synthesis lut_function=(A (B+!((D)+!C))+!A (B+(C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_291.init = 16'hdcec;
    FD1P3JX wr_data_i0_i5 (.D(n15839), .SP(DS18B20_rst), .PD(n16641), 
            .CK(clk_1us), .Q(wr_data[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam wr_data_i0_i5.GSR = "DISABLED";
    CCU2D cnt_1us_2272_add_4_21 (.A0(cnt_1us[19]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n24986), .S0(n85[19]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272_add_4_21.INIT0 = 16'hfaaa;
    defparam cnt_1us_2272_add_4_21.INIT1 = 16'h0000;
    defparam cnt_1us_2272_add_4_21.INJECT1_0 = "NO";
    defparam cnt_1us_2272_add_4_21.INJECT1_1 = "NO";
    CCU2D cnt_1us_2272_add_4_19 (.A0(cnt_1us[17]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_1us[18]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24985), .COUT(n24986), .S0(n85[17]), .S1(n85[18]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272_add_4_19.INIT0 = 16'hfaaa;
    defparam cnt_1us_2272_add_4_19.INIT1 = 16'hfaaa;
    defparam cnt_1us_2272_add_4_19.INJECT1_0 = "NO";
    defparam cnt_1us_2272_add_4_19.INJECT1_1 = "NO";
    LUT4 mux_1398_Mux_0_i3_4_lut_4_lut_3_lut (.A(flow_cnt[0]), .B(n29545), 
         .C(n29556), .Z(n4960[0])) /* synthesis lut_function=(A (B+!(C))+!A !(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(229[21] 252[28])
    defparam mux_1398_Mux_0_i3_4_lut_4_lut_3_lut.init = 16'h9b9b;
    LUT4 mux_1408_Mux_0_i3_4_lut_4_lut_4_lut (.A(flow_cnt[0]), .B(flow_cnt[1]), 
         .C(n29556), .D(cnt_1us_en), .Z(n4982[0])) /* synthesis lut_function=(A (B (D)+!B !(C))+!A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(229[21] 252[28])
    defparam mux_1408_Mux_0_i3_4_lut_4_lut_4_lut.init = 16'hce46;
    FD1P3JX bit_width_i0_i4 (.D(n15969), .SP(DS18B20_rst), .PD(n16641), 
            .CK(clk_1us), .Q(bit_width[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=13, LSE_RCOL=2, LSE_LLINE=376, LSE_RLINE=384 */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(179[10] 312[8])
    defparam bit_width_i0_i4.GSR = "DISABLED";
    LUT4 i1_4_lut_adj_292 (.A(n399[15]), .B(n33[15]), .C(n2131), .D(n15859), 
         .Z(org_data_15__N_714[15])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_292.init = 16'heca0;
    LUT4 mux_181_i1_3_lut (.A(org_data[0]), .B(n642[0]), .C(n33[15]), 
         .Z(data1_10__N_635[0])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(325[10] 328[8])
    defparam mux_181_i1_3_lut.init = 16'hcaca;
    LUT4 i1_3_lut_4_lut_adj_293 (.A(n29605), .B(n29586), .C(n29603), .D(wr_data[7]), 
         .Z(wr_data_7__N_730[7])) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_3_lut_4_lut_adj_293.init = 16'hfef0;
    LUT4 i1_2_lut_rep_283_3_lut_4_lut (.A(n15713), .B(n15754), .C(cnt_1us[5]), 
         .D(cnt_1us[19]), .Z(n29559)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(241[37:53])
    defparam i1_2_lut_rep_283_3_lut_4_lut.init = 16'hfffe;
    LUT4 i2_3_lut_4_lut_adj_294 (.A(n29618), .B(wr_cnt[3]), .C(n30946), 
         .D(n21345), .Z(n27606)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;
    defparam i2_3_lut_4_lut_adj_294.init = 16'h0002;
    LUT4 i2_2_lut_rep_327 (.A(n2113), .B(n2128), .Z(n29603)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i2_2_lut_rep_327.init = 16'heeee;
    LUT4 i1_2_lut_3_lut_4_lut_adj_295 (.A(n2113), .B(n2128), .C(n2125), 
         .D(n2122), .Z(n4_adj_1797)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_2_lut_3_lut_4_lut_adj_295.init = 16'hfffe;
    LUT4 i6_2_lut_rep_301_3_lut (.A(n2113), .B(n2128), .C(n2122), .Z(n29577)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i6_2_lut_rep_301_3_lut.init = 16'hfefe;
    LUT4 i1_2_lut_rep_328 (.A(n2113), .B(n2122), .Z(n29604)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_2_lut_rep_328.init = 16'heeee;
    LUT4 i2_3_lut_rep_302_4_lut (.A(n2113), .B(n2122), .C(n2128), .D(n29605), 
         .Z(n29578)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i2_3_lut_rep_302_4_lut.init = 16'hfffe;
    LUT4 i1_2_lut_rep_329 (.A(n2131), .B(n2125), .Z(n29605)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_2_lut_rep_329.init = 16'heeee;
    LUT4 i2_3_lut_3_lut (.A(n29642), .B(n21264), .C(n27699), .Z(n27700)) /* synthesis lut_function=(((C)+!B)+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(210[21:25])
    defparam i2_3_lut_3_lut.init = 16'hf7f7;
    LUT4 i1_4_lut_4_lut (.A(n29642), .B(n30946), .C(n27700), .D(n2110), 
         .Z(n27571)) /* synthesis lut_function=(A (C (D))+!A !(B+!(C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(210[21:25])
    defparam i1_4_lut_4_lut.init = 16'hb000;
    CCU2D add_179_7 (.A0(org_data[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(org_data[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n24940), .COUT(n24941), .S0(n642[5]), .S1(n642[6]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(327[18:40])
    defparam add_179_7.INIT0 = 16'ha555;
    defparam add_179_7.INIT1 = 16'ha555;
    defparam add_179_7.INJECT1_0 = "NO";
    defparam add_179_7.INJECT1_1 = "NO";
    LUT4 i1_2_lut_rep_331 (.A(n15713), .B(n15754), .Z(n29607)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(241[37:53])
    defparam i1_2_lut_rep_331.init = 16'heeee;
    PFUMX i22023 (.BLUT(n4_adj_1790), .ALUT(n5_adj_1789), .C0(wr_cnt[1]), 
          .Z(n28174));
    LUT4 i15327_3_lut_4_lut (.A(n29644), .B(n21294), .C(n29550), .D(n29659), 
         .Z(n21375)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;
    defparam i15327_3_lut_4_lut.init = 16'hfe00;
    CCU2D cnt_1us_2272_add_4_17 (.A0(cnt_1us[15]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_1us[16]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24984), .COUT(n24985), .S0(n85[15]), .S1(n85[16]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272_add_4_17.INIT0 = 16'hfaaa;
    defparam cnt_1us_2272_add_4_17.INIT1 = 16'hfaaa;
    defparam cnt_1us_2272_add_4_17.INJECT1_0 = "NO";
    defparam cnt_1us_2272_add_4_17.INJECT1_1 = "NO";
    CCU2D cnt_1us_2272_add_4_15 (.A0(cnt_1us[13]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_1us[14]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24983), .COUT(n24984), .S0(n85[13]), .S1(n85[14]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272_add_4_15.INIT0 = 16'hfaaa;
    defparam cnt_1us_2272_add_4_15.INIT1 = 16'hfaaa;
    defparam cnt_1us_2272_add_4_15.INJECT1_0 = "NO";
    defparam cnt_1us_2272_add_4_15.INJECT1_1 = "NO";
    LUT4 i1_4_lut_then_4_lut (.A(cmd_cnt[1]), .B(n29618), .C(n29558), 
         .D(wr_cnt[3]), .Z(n29721)) /* synthesis lut_function=(A (B (C+!(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_then_4_lut.init = 16'he4a8;
    PFUMX i23421 (.BLUT(n30947), .ALUT(n30948), .C0(wr_cnt[3]), .Z(cmd_cnt_3__N_710[2]));
    LUT4 i1_3_lut_4_lut_adj_296 (.A(n29605), .B(n29586), .C(n29603), .D(wr_data[3]), 
         .Z(wr_data_7__N_730[3])) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_3_lut_4_lut_adj_296.init = 16'hfef0;
    LUT4 i3413_4_lut (.A(n2095[4]), .B(next_state_2__N_565[1]), .C(n8_adj_1798), 
         .D(n2095[3]), .Z(n2122)) /* synthesis lut_function=(A ((C (D))+!B)+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i3413_4_lut.init = 16'he222;
    LUT4 i1_4_lut_adj_297 (.A(n399[4]), .B(org_data[4]), .C(n2131), .D(n15859), 
         .Z(org_data_15__N_714[4])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_297.init = 16'heca0;
    CCU2D cnt_1us_2272_add_4_13 (.A0(cnt_1us[11]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_1us[12]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24982), .COUT(n24983), .S0(n85[11]), .S1(n85[12]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272_add_4_13.INIT0 = 16'hfaaa;
    defparam cnt_1us_2272_add_4_13.INIT1 = 16'hfaaa;
    defparam cnt_1us_2272_add_4_13.INJECT1_0 = "NO";
    defparam cnt_1us_2272_add_4_13.INJECT1_1 = "NO";
    LUT4 i1_3_lut_4_lut_adj_298 (.A(n29605), .B(n29586), .C(wr_data[2]), 
         .D(n29577), .Z(wr_data_7__N_730[2])) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_3_lut_4_lut_adj_298.init = 16'hffe0;
    LUT4 i1_4_lut_adj_299 (.A(n399[10]), .B(org_data[10]), .C(n2131), 
         .D(n15859), .Z(org_data_15__N_714[10])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_299.init = 16'heca0;
    LUT4 i2013_2_lut_rep_269_4_lut (.A(n29696), .B(flow_cnt[2]), .C(flow_cnt[3]), 
         .D(n39_adj_1785), .Z(n29545)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(210[21:25])
    defparam i2013_2_lut_rep_269_4_lut.init = 16'h0400;
    LUT4 i1_4_lut_adj_300 (.A(cmd_cnt[3]), .B(cmd_cnt[1]), .C(cmd_cnt[0]), 
         .D(cmd_cnt[2]), .Z(n8_adj_1798)) /* synthesis lut_function=(A+(B (D)+!B (C+!(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_300.init = 16'hfebb;
    LUT4 i12_4_lut (.A(n2095[5]), .B(cmd_cnt[0]), .C(next_state_2__N_565[1]), 
         .D(n27422), .Z(n2125)) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i12_4_lut.init = 16'h3a0a;
    LUT4 mux_113_i3_4_lut_4_lut (.A(flow_cnt[2]), .B(n29662), .C(n27891), 
         .D(n16451), .Z(flow_cnt_3__N_673[2])) /* synthesis lut_function=(A (B (D)+!B ((D)+!C))+!A !((C+(D))+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(283[41:56])
    defparam mux_113_i3_4_lut_4_lut.init = 16'haa06;
    LUT4 i1_2_lut_3_lut_adj_301 (.A(n2110), .B(n29578), .C(cmd_cnt[0]), 
         .Z(n15812)) /* synthesis lut_function=(A (C)+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_2_lut_3_lut_adj_301.init = 16'he0e0;
    CCU2D cnt_1us_2272_add_4_11 (.A0(cnt_1us[9]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_1us[10]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24981), .COUT(n24982), .S0(n85[9]), .S1(n85[10]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272_add_4_11.INIT0 = 16'hfaaa;
    defparam cnt_1us_2272_add_4_11.INIT1 = 16'hfaaa;
    defparam cnt_1us_2272_add_4_11.INJECT1_0 = "NO";
    defparam cnt_1us_2272_add_4_11.INJECT1_1 = "NO";
    LUT4 i10142_3_lut_rep_342 (.A(n2095[3]), .B(n15071), .C(next_state_2__N_565[1]), 
         .Z(n29618)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i10142_3_lut_rep_342.init = 16'hcaca;
    CCU2D cnt_1us_2272_add_4_9 (.A0(cnt_1us[7]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_1us[8]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24980), .COUT(n24981), .S0(n85[7]), .S1(n85[8]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272_add_4_9.INIT0 = 16'hfaaa;
    defparam cnt_1us_2272_add_4_9.INIT1 = 16'hfaaa;
    defparam cnt_1us_2272_add_4_9.INJECT1_0 = "NO";
    defparam cnt_1us_2272_add_4_9.INJECT1_1 = "NO";
    CCU2D cnt_1us_2272_add_4_7 (.A0(cnt_1us[5]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_1us[6]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24979), .COUT(n24980), .S0(n85[5]), .S1(n85[6]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272_add_4_7.INIT0 = 16'hfaaa;
    defparam cnt_1us_2272_add_4_7.INIT1 = 16'hfaaa;
    defparam cnt_1us_2272_add_4_7.INJECT1_0 = "NO";
    defparam cnt_1us_2272_add_4_7.INJECT1_1 = "NO";
    LUT4 i1_2_lut_rep_326_4_lut (.A(n2095[3]), .B(n15071), .C(next_state_2__N_565[1]), 
         .D(wr_cnt[3]), .Z(n29602)) /* synthesis lut_function=(!(A (B (D)+!B (C+(D)))+!A (((D)+!C)+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_2_lut_rep_326_4_lut.init = 16'h00ca;
    CCU2D cnt_1us_2272_add_4_5 (.A0(cnt_1us[3]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_1us[4]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24978), .COUT(n24979), .S0(n85[3]), .S1(n85[4]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272_add_4_5.INIT0 = 16'hfaaa;
    defparam cnt_1us_2272_add_4_5.INIT1 = 16'hfaaa;
    defparam cnt_1us_2272_add_4_5.INJECT1_0 = "NO";
    defparam cnt_1us_2272_add_4_5.INJECT1_1 = "NO";
    LUT4 i1_2_lut_4_lut_adj_302 (.A(n2095[3]), .B(n15071), .C(next_state_2__N_565[1]), 
         .D(dq_N_797), .Z(n4_adj_1794)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_2_lut_4_lut_adj_302.init = 16'hca00;
    LUT4 i1_2_lut_rep_310_4_lut (.A(n2095[3]), .B(n15071), .C(next_state_2__N_565[1]), 
         .D(n2110), .Z(n29586)) /* synthesis lut_function=(A (B+((D)+!C))+!A (B (C+(D))+!B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_2_lut_rep_310_4_lut.init = 16'hffca;
    LUT4 i7495_3_lut_4_lut (.A(flow_cnt[3]), .B(flow_cnt[2]), .C(n29662), 
         .D(n13250), .Z(n7449)) /* synthesis lut_function=(A (((D)+!C)+!B)+!A !(((D)+!C)+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(283[41:56])
    defparam i7495_3_lut_4_lut.init = 16'haa6a;
    LUT4 i14458_2_lut (.A(n85[0]), .B(cnt_1us_en), .Z(n107[0])) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam i14458_2_lut.init = 16'h8888;
    LUT4 i3966_3_lut_4_lut (.A(n30946), .B(n29662), .C(n29663), .D(wr_cnt[2]), 
         .Z(n5028[2])) /* synthesis lut_function=(A (D)+!A !(B (C (D)+!C !(D))+!B !(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(229[21] 252[28])
    defparam i3966_3_lut_4_lut.init = 16'hbf40;
    LUT4 i2_3_lut_adj_303 (.A(n2095[4]), .B(n2095[2]), .C(n2095[6]), .Z(n15071)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i2_3_lut_adj_303.init = 16'hfefe;
    LUT4 i3964_3_lut_4_lut (.A(n30946), .B(n29662), .C(wr_cnt[0]), .D(wr_cnt[1]), 
         .Z(n5028[1])) /* synthesis lut_function=(A (D)+!A !(B (C (D)+!C !(D))+!B !(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(229[21] 252[28])
    defparam i3964_3_lut_4_lut.init = 16'hbf40;
    LUT4 i1_4_lut_adj_304 (.A(n399[9]), .B(org_data[9]), .C(n2131), .D(n15859), 
         .Z(org_data_15__N_714[9])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_304.init = 16'heca0;
    LUT4 i1_4_lut_adj_305 (.A(n399[8]), .B(org_data[8]), .C(n2131), .D(n15859), 
         .Z(org_data_15__N_714[8])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_305.init = 16'heca0;
    LUT4 i3_4_lut_adj_306 (.A(n5_adj_1799), .B(n29716), .C(flow_cnt[2]), 
         .D(n15832), .Z(flow_cnt_3__N_577[2])) /* synthesis lut_function=(A+(B+(C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i3_4_lut_adj_306.init = 16'hfeee;
    LUT4 i1_4_lut_adj_307 (.A(n399[7]), .B(org_data[7]), .C(n2131), .D(n15859), 
         .Z(org_data_15__N_714[7])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_307.init = 16'heca0;
    LUT4 i1_4_lut_adj_308 (.A(n399[3]), .B(org_data[3]), .C(n2131), .D(n15859), 
         .Z(org_data_15__N_714[3])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_308.init = 16'heca0;
    LUT4 i1_3_lut_4_lut_adj_309 (.A(n29605), .B(n29586), .C(n29604), .D(wr_data[6]), 
         .Z(wr_data_7__N_730[6])) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_3_lut_4_lut_adj_309.init = 16'hfef0;
    LUT4 i1_4_lut_adj_310 (.A(n7448), .B(flow_cnt_3__N_673[2]), .C(n27571), 
         .D(n2131), .Z(n5_adj_1799)) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_310.init = 16'heca0;
    CCU2D cnt_1us_2272_add_4_3 (.A0(cnt_1us[1]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_1us[2]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24977), .COUT(n24978), .S0(n85[1]), .S1(n85[2]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272_add_4_3.INIT0 = 16'hfaaa;
    defparam cnt_1us_2272_add_4_3.INIT1 = 16'hfaaa;
    defparam cnt_1us_2272_add_4_3.INJECT1_0 = "NO";
    defparam cnt_1us_2272_add_4_3.INJECT1_1 = "NO";
    LUT4 i1_4_lut_adj_311 (.A(n399[2]), .B(org_data[2]), .C(n2131), .D(n15859), 
         .Z(org_data_15__N_714[2])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_311.init = 16'heca0;
    CCU2D cnt_1us_2272_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_1us[0]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .COUT(n24977), .S1(n85[0]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(96[20:34])
    defparam cnt_1us_2272_add_4_1.INIT0 = 16'hF000;
    defparam cnt_1us_2272_add_4_1.INIT1 = 16'h0555;
    defparam cnt_1us_2272_add_4_1.INJECT1_0 = "NO";
    defparam cnt_1us_2272_add_4_1.INJECT1_1 = "NO";
    LUT4 i14787_2_lut_4_lut (.A(n21329), .B(n29643), .C(n29644), .D(n29619), 
         .Z(n4461[3])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(D))+!A (B+!(C (D))))) */ ;
    defparam i14787_2_lut_4_lut.init = 16'h3a00;
    LUT4 i1_4_lut_adj_312 (.A(n399[1]), .B(org_data[1]), .C(n2131), .D(n15859), 
         .Z(org_data_15__N_714[1])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_312.init = 16'heca0;
    LUT4 i1_4_lut_adj_313 (.A(n399[6]), .B(org_data[6]), .C(n2131), .D(n15859), 
         .Z(org_data_15__N_714[6])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_313.init = 16'heca0;
    PFUMX mux_1407_i1 (.BLUT(n4982[0]), .ALUT(n4974[0]), .C0(n28080), 
          .Z(cnt_1us_en_N_787));
    LUT4 i2_4_lut_adj_314 (.A(n29618), .B(n4_adj_1797), .C(n4_adj_1800), 
         .D(dq_N_813), .Z(dq_N_811)) /* synthesis lut_function=(A (B+(C+(D)))+!A (B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i2_4_lut_adj_314.init = 16'hfefc;
    LUT4 i1_4_lut_adj_315 (.A(n28799), .B(n2131), .C(n27889), .D(n4_adj_1788), 
         .Z(n4_adj_1800)) /* synthesis lut_function=(A+(B (C+!(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_315.init = 16'heaee;
    LUT4 i14868_4_lut (.A(n20687), .B(n29644), .C(n27765), .D(n29700), 
         .Z(dq_N_813)) /* synthesis lut_function=(A (B+!(C+(D)))+!A (B+!(C))) */ ;
    defparam i14868_4_lut.init = 16'hcdcf;
    LUT4 i21744_3_lut (.A(flow_cnt[0]), .B(flow_cnt[3]), .C(flow_cnt[1]), 
         .Z(n27889)) /* synthesis lut_function=(A (B+(C))+!A (B)) */ ;
    defparam i21744_3_lut.init = 16'hecec;
    LUT4 i14785_2_lut_4_lut (.A(n21329), .B(n29643), .C(n29644), .D(n29657), 
         .Z(n4461[1])) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(D))+!A (B+!(C (D))))) */ ;
    defparam i14785_2_lut_4_lut.init = 16'h3a00;
    PFUMX mux_2013_i1 (.BLUT(n2), .ALUT(n4960[0]), .C0(n28052), .Z(n7446));
    LUT4 i3082_1_lut (.A(dq_N_757), .Z(n8566)) /* synthesis lut_function=(!(A)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(167[1] 313[4])
    defparam i3082_1_lut.init = 16'h5555;
    LUT4 i1_4_lut_else_4_lut (.A(cmd_cnt[1]), .B(n29618), .C(n29558), 
         .Z(n29720)) /* synthesis lut_function=(A (B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_else_4_lut.init = 16'ha8a8;
    LUT4 i3_4_lut_adj_316 (.A(n5_adj_1801), .B(n3_adj_1802), .C(flow_cnt[1]), 
         .D(n15832), .Z(flow_cnt_3__N_577[1])) /* synthesis lut_function=(A+(B+(C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i3_4_lut_adj_316.init = 16'hfeee;
    LUT4 i22271_2_lut_3_lut (.A(n29642), .B(n39_adj_1785), .C(flow_cnt[1]), 
         .Z(n28052)) /* synthesis lut_function=(A (B+!(C))+!A !(C)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(184[17] 220[24])
    defparam i22271_2_lut_3_lut.init = 16'h8f8f;
    CCU2D add_179_3 (.A0(org_data[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(org_data[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n24938), .COUT(n24939), .S0(n642[1]), .S1(n642[2]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(327[18:40])
    defparam add_179_3.INIT0 = 16'ha555;
    defparam add_179_3.INIT1 = 16'ha555;
    defparam add_179_3.INJECT1_0 = "NO";
    defparam add_179_3.INJECT1_1 = "NO";
    LUT4 mux_181_i11_3_lut (.A(org_data[10]), .B(n642[10]), .C(n33[15]), 
         .Z(data1_10__N_635[10])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(325[10] 328[8])
    defparam mux_181_i11_3_lut.init = 16'hcaca;
    LUT4 mux_181_i10_3_lut (.A(org_data[9]), .B(n642[9]), .C(n33[15]), 
         .Z(data1_10__N_635[9])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(325[10] 328[8])
    defparam mux_181_i10_3_lut.init = 16'hcaca;
    LUT4 mux_181_i9_3_lut (.A(org_data[8]), .B(n642[8]), .C(n33[15]), 
         .Z(data1_10__N_635[8])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(325[10] 328[8])
    defparam mux_181_i9_3_lut.init = 16'hcaca;
    LUT4 mux_181_i8_3_lut (.A(org_data[7]), .B(n642[7]), .C(n33[15]), 
         .Z(data1_10__N_635[7])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(325[10] 328[8])
    defparam mux_181_i8_3_lut.init = 16'hcaca;
    LUT4 mux_181_i7_3_lut (.A(org_data[6]), .B(n642[6]), .C(n33[15]), 
         .Z(data1_10__N_635[6])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(325[10] 328[8])
    defparam mux_181_i7_3_lut.init = 16'hcaca;
    LUT4 mux_181_i6_3_lut (.A(org_data[5]), .B(n642[5]), .C(n33[15]), 
         .Z(data1_10__N_635[5])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(325[10] 328[8])
    defparam mux_181_i6_3_lut.init = 16'hcaca;
    LUT4 mux_181_i5_3_lut (.A(org_data[4]), .B(n642[4]), .C(n33[15]), 
         .Z(data1_10__N_635[4])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(325[10] 328[8])
    defparam mux_181_i5_3_lut.init = 16'hcaca;
    LUT4 mux_181_i4_3_lut (.A(org_data[3]), .B(n642[3]), .C(n33[15]), 
         .Z(data1_10__N_635[3])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(325[10] 328[8])
    defparam mux_181_i4_3_lut.init = 16'hcaca;
    LUT4 mux_181_i3_3_lut (.A(org_data[2]), .B(n642[2]), .C(n33[15]), 
         .Z(data1_10__N_635[2])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(325[10] 328[8])
    defparam mux_181_i3_3_lut.init = 16'hcaca;
    LUT4 mux_181_i2_3_lut (.A(org_data[1]), .B(n642[1]), .C(n33[15]), 
         .Z(data1_10__N_635[1])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(325[10] 328[8])
    defparam mux_181_i2_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_adj_317 (.A(n7447), .B(flow_cnt_3__N_673[1]), .C(n27571), 
         .D(n2131), .Z(n5_adj_1801)) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_317.init = 16'heca0;
    LUT4 select_559_Select_1_i3_4_lut (.A(n4461[1]), .B(n29618), .C(flow_cnt[1]), 
         .D(n7577), .Z(n3_adj_1802)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam select_559_Select_1_i3_4_lut.init = 16'hc088;
    LUT4 i1_4_lut_adj_318 (.A(cmd_cnt[3]), .B(n29558), .C(n29618), .D(n30933), 
         .Z(cmd_cnt_3__N_646[3])) /* synthesis lut_function=(A (B+!((D)+!C))+!A (C (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_318.init = 16'hd8a8;
    LUT4 i1_4_lut_adj_319 (.A(cmd_cnt_3__N_710[2]), .B(cmd_cnt[2]), .C(n29618), 
         .D(n29558), .Z(cmd_cnt_3__N_646[2])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_319.init = 16'heca0;
    LUT4 i12_4_lut_adj_320 (.A(n29620), .B(n29558), .C(wr_cnt[3]), .D(n4), 
         .Z(wr_cnt_3__N_581[3])) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i12_4_lut_adj_320.init = 16'hcac0;
    LUT4 i1_4_lut_adj_321 (.A(n5028[2]), .B(wr_cnt[2]), .C(n29602), .D(n29558), 
         .Z(wr_cnt_3__N_581[2])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_321.init = 16'heca0;
    LUT4 i1_4_lut_adj_322 (.A(n5028[1]), .B(wr_cnt[1]), .C(n29602), .D(n29558), 
         .Z(wr_cnt_3__N_581[1])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_322.init = 16'heca0;
    LUT4 i1_4_lut_adj_323 (.A(rd_cnt[4]), .B(n15859), .C(n27530), .D(n8456), 
         .Z(rd_cnt_4__N_585[4])) /* synthesis lut_function=(A (B+!((D)+!C))+!A (C (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_323.init = 16'hd8a8;
    LUT4 i1_4_lut_adj_324 (.A(rd_cnt[3]), .B(n15859), .C(n27530), .D(n29539), 
         .Z(rd_cnt_4__N_585[3])) /* synthesis lut_function=(A (B+!((D)+!C))+!A (C (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_324.init = 16'hd8a8;
    LUT4 i1_4_lut_adj_325 (.A(rd_cnt[2]), .B(n15859), .C(n27530), .D(n29540), 
         .Z(rd_cnt_4__N_585[2])) /* synthesis lut_function=(A (B+!((D)+!C))+!A (C (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_325.init = 16'hd8a8;
    LUT4 i1_4_lut_adj_326 (.A(rd_cnt[1]), .B(n15859), .C(n27530), .D(n29542), 
         .Z(rd_cnt_4__N_585[1])) /* synthesis lut_function=(A (B+!((D)+!C))+!A (C (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_326.init = 16'hd8a8;
    LUT4 i1_4_lut_adj_327 (.A(rd_data_15__N_685[15]), .B(rd_data[15]), .C(n2131), 
         .D(n15859), .Z(rd_data_15__N_603[15])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_327.init = 16'heca0;
    LUT4 i3356_3_lut (.A(DS18B20_bus_out), .B(rd_data[15]), .C(n15156), 
         .Z(rd_data_15__N_685[15])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(279[21] 302[28])
    defparam i3356_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_adj_328 (.A(rd_data_15__N_685[14]), .B(rd_data[14]), .C(n2131), 
         .D(n15859), .Z(rd_data_15__N_603[14])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_328.init = 16'heca0;
    LUT4 i3358_3_lut (.A(rd_data[15]), .B(rd_data[14]), .C(n15156), .Z(rd_data_15__N_685[14])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(279[21] 302[28])
    defparam i3358_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_adj_329 (.A(rd_data_15__N_685[13]), .B(rd_data[13]), .C(n2131), 
         .D(n15859), .Z(rd_data_15__N_603[13])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_329.init = 16'heca0;
    LUT4 i3360_3_lut (.A(rd_data[14]), .B(rd_data[13]), .C(n15156), .Z(rd_data_15__N_685[13])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(279[21] 302[28])
    defparam i3360_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_adj_330 (.A(rd_data_15__N_685[12]), .B(rd_data[12]), .C(n2131), 
         .D(n15859), .Z(rd_data_15__N_603[12])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_330.init = 16'heca0;
    LUT4 i3362_3_lut (.A(rd_data[13]), .B(rd_data[12]), .C(n15156), .Z(rd_data_15__N_685[12])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(279[21] 302[28])
    defparam i3362_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_adj_331 (.A(rd_data_15__N_685[11]), .B(rd_data[11]), .C(n2131), 
         .D(n15859), .Z(rd_data_15__N_603[11])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_331.init = 16'heca0;
    LUT4 i3364_3_lut (.A(rd_data[12]), .B(rd_data[11]), .C(n15156), .Z(rd_data_15__N_685[11])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(279[21] 302[28])
    defparam i3364_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_adj_332 (.A(rd_data_15__N_685[10]), .B(rd_data[10]), .C(n2131), 
         .D(n15859), .Z(rd_data_15__N_603[10])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_332.init = 16'heca0;
    LUT4 i3366_3_lut (.A(rd_data[11]), .B(rd_data[10]), .C(n15156), .Z(rd_data_15__N_685[10])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(279[21] 302[28])
    defparam i3366_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_adj_333 (.A(rd_data_15__N_685[9]), .B(rd_data[9]), .C(n2131), 
         .D(n15859), .Z(rd_data_15__N_603[9])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_333.init = 16'heca0;
    LUT4 i3368_3_lut (.A(rd_data[10]), .B(rd_data[9]), .C(n15156), .Z(rd_data_15__N_685[9])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(279[21] 302[28])
    defparam i3368_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_adj_334 (.A(rd_data_15__N_685[8]), .B(rd_data[8]), .C(n2131), 
         .D(n15859), .Z(rd_data_15__N_603[8])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_334.init = 16'heca0;
    LUT4 i3370_3_lut (.A(rd_data[9]), .B(rd_data[8]), .C(n15156), .Z(rd_data_15__N_685[8])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(279[21] 302[28])
    defparam i3370_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_adj_335 (.A(rd_data_15__N_685[7]), .B(rd_data[7]), .C(n2131), 
         .D(n15859), .Z(rd_data_15__N_603[7])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_335.init = 16'heca0;
    LUT4 i3372_3_lut (.A(rd_data[8]), .B(rd_data[7]), .C(n15156), .Z(rd_data_15__N_685[7])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(279[21] 302[28])
    defparam i3372_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_adj_336 (.A(rd_data_15__N_685[6]), .B(rd_data[6]), .C(n2131), 
         .D(n15859), .Z(rd_data_15__N_603[6])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_336.init = 16'heca0;
    LUT4 i3374_3_lut (.A(rd_data[7]), .B(rd_data[6]), .C(n15156), .Z(rd_data_15__N_685[6])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(279[21] 302[28])
    defparam i3374_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_adj_337 (.A(rd_data_15__N_685[5]), .B(rd_data[5]), .C(n2131), 
         .D(n15859), .Z(rd_data_15__N_603[5])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_337.init = 16'heca0;
    LUT4 i3376_3_lut (.A(rd_data[6]), .B(rd_data[5]), .C(n15156), .Z(rd_data_15__N_685[5])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(279[21] 302[28])
    defparam i3376_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_adj_338 (.A(rd_data_15__N_685[4]), .B(rd_data[4]), .C(n2131), 
         .D(n15859), .Z(rd_data_15__N_603[4])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_338.init = 16'heca0;
    LUT4 i3378_3_lut (.A(rd_data[5]), .B(rd_data[4]), .C(n15156), .Z(rd_data_15__N_685[4])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(279[21] 302[28])
    defparam i3378_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_adj_339 (.A(rd_data_15__N_685[3]), .B(rd_data[3]), .C(n2131), 
         .D(n15859), .Z(rd_data_15__N_603[3])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_339.init = 16'heca0;
    LUT4 i3380_3_lut (.A(rd_data[4]), .B(rd_data[3]), .C(n15156), .Z(rd_data_15__N_685[3])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(279[21] 302[28])
    defparam i3380_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_adj_340 (.A(rd_data_15__N_685[2]), .B(rd_data[2]), .C(n2131), 
         .D(n15859), .Z(rd_data_15__N_603[2])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_340.init = 16'heca0;
    LUT4 i3382_3_lut (.A(rd_data[3]), .B(rd_data[2]), .C(n15156), .Z(rd_data_15__N_685[2])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(279[21] 302[28])
    defparam i3382_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_adj_341 (.A(rd_data_15__N_685[1]), .B(rd_data[1]), .C(n2131), 
         .D(n15859), .Z(rd_data_15__N_603[1])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_341.init = 16'heca0;
    LUT4 i3384_3_lut (.A(rd_data[2]), .B(rd_data[1]), .C(n15156), .Z(rd_data_15__N_685[1])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(279[21] 302[28])
    defparam i3384_3_lut.init = 16'hcaca;
    LUT4 i3_4_lut_adj_342 (.A(n5_adj_1803), .B(n3_adj_1804), .C(flow_cnt[3]), 
         .D(n15832), .Z(flow_cnt_3__N_577[3])) /* synthesis lut_function=(A+(B+(C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i3_4_lut_adj_342.init = 16'hfeee;
    LUT4 i1_4_lut_adj_343 (.A(n7449), .B(flow_cnt_3__N_673[3]), .C(n27571), 
         .D(n2131), .Z(n5_adj_1803)) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_343.init = 16'heca0;
    LUT4 select_559_Select_3_i3_4_lut (.A(n4461[3]), .B(n29618), .C(flow_cnt[3]), 
         .D(n7577), .Z(n3_adj_1804)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam select_559_Select_3_i3_4_lut.init = 16'hc088;
    LUT4 mux_113_i4_4_lut (.A(flow_cnt[3]), .B(n29619), .C(n16451), .D(n27891), 
         .Z(flow_cnt_3__N_673[3])) /* synthesis lut_function=(A (B (C+!(D))+!B (C))+!A !((C+(D))+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(304[22] 308[20])
    defparam mux_113_i4_4_lut.init = 16'ha0ac;
    LUT4 i1_4_lut_adj_344 (.A(n399[0]), .B(org_data[0]), .C(n2131), .D(n15859), 
         .Z(org_data_15__N_714[0])) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_4_lut_adj_344.init = 16'heca0;
    LUT4 i13_4_lut (.A(n2095[7]), .B(n27897), .C(next_state_2__N_565[1]), 
         .D(n4_adj_1805), .Z(n2131)) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i13_4_lut.init = 16'h3a0a;
    LUT4 i1_2_lut_adj_345 (.A(n2095[3]), .B(cmd_cnt[2]), .Z(n4_adj_1805)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i1_2_lut_adj_345.init = 16'h8888;
    LUT4 i12_4_lut_adj_346 (.A(n2095[6]), .B(cmd_cnt[0]), .C(next_state_2__N_565[1]), 
         .D(n27422), .Z(n2128)) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i12_4_lut_adj_346.init = 16'hca0a;
    LUT4 i7494_4_lut (.A(n8902), .B(n29545), .C(n9572), .D(flow_cnt[1]), 
         .Z(n13250)) /* synthesis lut_function=(A (B+(C+!(D)))+!A (B+(C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(184[17] 220[24])
    defparam i7494_4_lut.init = 16'hfcee;
    LUT4 i21752_3_lut (.A(cmd_cnt[3]), .B(cmd_cnt[0]), .C(cmd_cnt[1]), 
         .Z(n27897)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i21752_3_lut.init = 16'hfefe;
    LUT4 i2_4_lut_adj_347 (.A(cmd_cnt[2]), .B(n2095[3]), .C(cmd_cnt[3]), 
         .D(cmd_cnt[1]), .Z(n27422)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i2_4_lut_adj_347.init = 16'h0400;
    LUT4 i3400_2_lut (.A(n29556), .B(flow_cnt[0]), .Z(n8902)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(184[17] 220[24])
    defparam i3400_2_lut.init = 16'h4444;
    LUT4 i3417_4_lut (.A(n2095[2]), .B(next_state_2__N_574[1]), .C(next_state_2__N_565[1]), 
         .D(n2095[1]), .Z(n2113)) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i3417_4_lut.init = 16'hce0a;
    LUT4 i3419_4_lut (.A(n2095[1]), .B(next_state_2__N_565[1]), .C(next_state_2__N_574[1]), 
         .D(n9513), .Z(n2110)) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(111[5] 162[12])
    defparam i3419_4_lut.init = 16'hce0a;
    CCU2D add_179_5 (.A0(org_data[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(org_data[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n24939), .COUT(n24940), .S0(n642[3]), .S1(n642[4]));   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(327[18:40])
    defparam add_179_5.INIT0 = 16'ha555;
    defparam add_179_5.INIT1 = 16'ha555;
    defparam add_179_5.INJECT1_0 = "NO";
    defparam add_179_5.INJECT1_1 = "NO";
    LUT4 i3954_3_lut (.A(dq_N_809), .B(DS18B20_bus_out), .C(flow_cnt[0]), 
         .Z(n9572)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/ds18b20/ds18b20_dri.v(184[17] 220[24])
    defparam i3954_3_lut.init = 16'hcaca;
    
endmodule
//
// Verilog Description of module PUR
// module not written out since it is a black-box. 
//

//
// Verilog Description of module \uart_recv(CLK_FREQ=12000000,UART_BPS=115200) 
//

module \uart_recv(CLK_FREQ=12000000,UART_BPS=115200)  (sys_clk_c, rx_flag, 
            uart_en_R, uart_rx_bus_c, sys_clk_c_enable_47, n31, n29636, 
            GND_net, uart_data_R, n29575) /* synthesis syn_module_defined=1 */ ;
    input sys_clk_c;
    output rx_flag;
    output uart_en_R;
    input uart_rx_bus_c;
    input sys_clk_c_enable_47;
    output n31;
    output n29636;
    input GND_net;
    output [7:0]uart_data_R;
    output n29575;
    
    wire sys_clk_c /* synthesis SET_AS_NETWORK=sys_clk_c, is_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(12[19:26])
    
    wire uart_rxd_d1, uart_rxd_d0, n16520, uart_data_7__N_460;
    wire [7:0]rxdata;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(48[12:18])
    
    wire n7993, n15961, rx_flag_N_461;
    wire [15:0]n2335;
    
    wire sys_clk_c_enable_62, n27387;
    wire [15:0]clk_cnt;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(45[12:19])
    
    wire n27386, n6, n15, n14, n29689, n29597, n29690, n29635, 
        n29598, n25063;
    wire [15:0]n69;
    
    wire n25062, n25061, n25060, n25059, n25058, n25057, n25056, 
        n15798, n15793, n15951, n15945, n15948, n15790, n15787, 
        n16597, n16628, n27755, n27754, n27688, n27689, n27743, 
        n27692, n25399, n4, n27714, n27704;
    
    FD1S3AX uart_rxd_d1_52 (.D(uart_rxd_d0), .CK(sys_clk_c), .Q(uart_rxd_d1)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=339, LSE_RLINE=347 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(65[10] 68[8])
    defparam uart_rxd_d1_52.GSR = "ENABLED";
    FD1S3AX rx_flag_53 (.D(n16520), .CK(sys_clk_c), .Q(rx_flag)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=339, LSE_RLINE=347 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(75[10] 82[8])
    defparam rx_flag_53.GSR = "ENABLED";
    FD1S3AX uart_done_58 (.D(uart_data_7__N_460), .CK(sys_clk_c), .Q(uart_en_R)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=339, LSE_RLINE=347 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(137[10] 144[8])
    defparam uart_done_58.GSR = "ENABLED";
    FD1S3AX uart_rxd_d0_51 (.D(uart_rx_bus_c), .CK(sys_clk_c), .Q(uart_rxd_d0)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=339, LSE_RLINE=347 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(65[10] 68[8])
    defparam uart_rxd_d0_51.GSR = "ENABLED";
    FD1P3IX rxdata__i0 (.D(n15961), .SP(sys_clk_c_enable_47), .CD(n7993), 
            .CK(sys_clk_c), .Q(rxdata[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=339, LSE_RLINE=347 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(111[10] 128[24])
    defparam rxdata__i0.GSR = "ENABLED";
    LUT4 uart_rxd_d1_I_0_2_lut (.A(uart_rxd_d1), .B(uart_rxd_d0), .Z(rx_flag_N_461)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(57[22:50])
    defparam uart_rxd_d1_I_0_2_lut.init = 16'h2222;
    FD1P3JX rx_cnt_FSM_i0 (.D(n2335[15]), .SP(sys_clk_c_enable_62), .PD(n7993), 
            .CK(sys_clk_c), .Q(n2335[0]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(98[28:41])
    defparam rx_cnt_FSM_i0.GSR = "ENABLED";
    LUT4 i3_4_lut (.A(n27387), .B(clk_cnt[4]), .C(clk_cnt[5]), .D(clk_cnt[2]), 
         .Z(n31)) /* synthesis lut_function=(A+!(B (C (D)))) */ ;
    defparam i3_4_lut.init = 16'hbfff;
    LUT4 i4_4_lut (.A(clk_cnt[1]), .B(n27386), .C(clk_cnt[3]), .D(n6), 
         .Z(n27387)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(92[17:38])
    defparam i4_4_lut.init = 16'hfffe;
    LUT4 i1_2_lut (.A(clk_cnt[0]), .B(clk_cnt[6]), .Z(n6)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(92[17:38])
    defparam i1_2_lut.init = 16'heeee;
    LUT4 i8_4_lut (.A(n15), .B(clk_cnt[13]), .C(n14), .D(clk_cnt[8]), 
         .Z(n27386)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(92[17:38])
    defparam i8_4_lut.init = 16'hfffe;
    LUT4 i6_4_lut (.A(clk_cnt[14]), .B(clk_cnt[15]), .C(clk_cnt[9]), .D(clk_cnt[7]), 
         .Z(n15)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(92[17:38])
    defparam i6_4_lut.init = 16'hfffe;
    LUT4 i5_3_lut (.A(clk_cnt[12]), .B(clk_cnt[10]), .C(clk_cnt[11]), 
         .Z(n14)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(92[17:38])
    defparam i5_3_lut.init = 16'hfefe;
    LUT4 i1_2_lut_rep_413 (.A(n2335[6]), .B(n2335[7]), .Z(n29689)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_2_lut_rep_413.init = 16'heeee;
    LUT4 i1_2_lut_rep_360_3_lut (.A(n2335[6]), .B(n2335[7]), .C(n2335[8]), 
         .Z(n29636)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_2_lut_rep_360_3_lut.init = 16'hfefe;
    LUT4 i1_2_lut_rep_321_3_lut_4_lut (.A(n2335[6]), .B(n2335[7]), .C(n2335[5]), 
         .D(n2335[8]), .Z(n29597)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_2_lut_rep_321_3_lut_4_lut.init = 16'hfffe;
    LUT4 i1_2_lut_rep_414 (.A(n2335[3]), .B(n2335[2]), .Z(n29690)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_2_lut_rep_414.init = 16'heeee;
    LUT4 i1_2_lut_rep_359_3_lut (.A(n2335[3]), .B(n2335[2]), .C(n2335[1]), 
         .Z(n29635)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_2_lut_rep_359_3_lut.init = 16'hfefe;
    LUT4 i1_2_lut_rep_322_3_lut_4_lut (.A(n2335[3]), .B(n2335[2]), .C(n2335[4]), 
         .D(n2335[1]), .Z(n29598)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_2_lut_rep_322_3_lut_4_lut.init = 16'hfffe;
    CCU2D clk_cnt_2268_add_4_17 (.A0(clk_cnt[15]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n25063), .S0(n69[15]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268_add_4_17.INIT0 = 16'hfaaa;
    defparam clk_cnt_2268_add_4_17.INIT1 = 16'h0000;
    defparam clk_cnt_2268_add_4_17.INJECT1_0 = "NO";
    defparam clk_cnt_2268_add_4_17.INJECT1_1 = "NO";
    CCU2D clk_cnt_2268_add_4_15 (.A0(clk_cnt[13]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clk_cnt[14]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25062), .COUT(n25063), .S0(n69[13]), .S1(n69[14]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268_add_4_15.INIT0 = 16'hfaaa;
    defparam clk_cnt_2268_add_4_15.INIT1 = 16'hfaaa;
    defparam clk_cnt_2268_add_4_15.INJECT1_0 = "NO";
    defparam clk_cnt_2268_add_4_15.INJECT1_1 = "NO";
    CCU2D clk_cnt_2268_add_4_13 (.A0(clk_cnt[11]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clk_cnt[12]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25061), .COUT(n25062), .S0(n69[11]), .S1(n69[12]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268_add_4_13.INIT0 = 16'hfaaa;
    defparam clk_cnt_2268_add_4_13.INIT1 = 16'hfaaa;
    defparam clk_cnt_2268_add_4_13.INJECT1_0 = "NO";
    defparam clk_cnt_2268_add_4_13.INJECT1_1 = "NO";
    CCU2D clk_cnt_2268_add_4_11 (.A0(clk_cnt[9]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clk_cnt[10]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25060), .COUT(n25061), .S0(n69[9]), .S1(n69[10]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268_add_4_11.INIT0 = 16'hfaaa;
    defparam clk_cnt_2268_add_4_11.INIT1 = 16'hfaaa;
    defparam clk_cnt_2268_add_4_11.INJECT1_0 = "NO";
    defparam clk_cnt_2268_add_4_11.INJECT1_1 = "NO";
    CCU2D clk_cnt_2268_add_4_9 (.A0(clk_cnt[7]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clk_cnt[8]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25059), .COUT(n25060), .S0(n69[7]), .S1(n69[8]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268_add_4_9.INIT0 = 16'hfaaa;
    defparam clk_cnt_2268_add_4_9.INIT1 = 16'hfaaa;
    defparam clk_cnt_2268_add_4_9.INJECT1_0 = "NO";
    defparam clk_cnt_2268_add_4_9.INJECT1_1 = "NO";
    CCU2D clk_cnt_2268_add_4_7 (.A0(clk_cnt[5]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clk_cnt[6]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25058), .COUT(n25059), .S0(n69[5]), .S1(n69[6]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268_add_4_7.INIT0 = 16'hfaaa;
    defparam clk_cnt_2268_add_4_7.INIT1 = 16'hfaaa;
    defparam clk_cnt_2268_add_4_7.INJECT1_0 = "NO";
    defparam clk_cnt_2268_add_4_7.INJECT1_1 = "NO";
    CCU2D clk_cnt_2268_add_4_5 (.A0(clk_cnt[3]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clk_cnt[4]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25057), .COUT(n25058), .S0(n69[3]), .S1(n69[4]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268_add_4_5.INIT0 = 16'hfaaa;
    defparam clk_cnt_2268_add_4_5.INIT1 = 16'hfaaa;
    defparam clk_cnt_2268_add_4_5.INJECT1_0 = "NO";
    defparam clk_cnt_2268_add_4_5.INJECT1_1 = "NO";
    CCU2D clk_cnt_2268_add_4_3 (.A0(clk_cnt[1]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clk_cnt[2]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25056), .COUT(n25057), .S0(n69[1]), .S1(n69[2]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268_add_4_3.INIT0 = 16'hfaaa;
    defparam clk_cnt_2268_add_4_3.INIT1 = 16'hfaaa;
    defparam clk_cnt_2268_add_4_3.INJECT1_0 = "NO";
    defparam clk_cnt_2268_add_4_3.INJECT1_1 = "NO";
    CCU2D clk_cnt_2268_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clk_cnt[0]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .COUT(n25056), .S1(n69[0]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268_add_4_1.INIT0 = 16'hF000;
    defparam clk_cnt_2268_add_4_1.INIT1 = 16'h0555;
    defparam clk_cnt_2268_add_4_1.INJECT1_0 = "NO";
    defparam clk_cnt_2268_add_4_1.INJECT1_1 = "NO";
    FD1P3IX rxdata__i7 (.D(n15798), .SP(sys_clk_c_enable_47), .CD(n7993), 
            .CK(sys_clk_c), .Q(rxdata[7])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=339, LSE_RLINE=347 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(111[10] 128[24])
    defparam rxdata__i7.GSR = "ENABLED";
    FD1P3IX rxdata__i6 (.D(n15793), .SP(sys_clk_c_enable_47), .CD(n7993), 
            .CK(sys_clk_c), .Q(rxdata[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=339, LSE_RLINE=347 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(111[10] 128[24])
    defparam rxdata__i6.GSR = "ENABLED";
    FD1P3IX rxdata__i5 (.D(n15951), .SP(sys_clk_c_enable_47), .CD(n7993), 
            .CK(sys_clk_c), .Q(rxdata[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=339, LSE_RLINE=347 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(111[10] 128[24])
    defparam rxdata__i5.GSR = "ENABLED";
    FD1P3IX rxdata__i4 (.D(n15945), .SP(sys_clk_c_enable_47), .CD(n7993), 
            .CK(sys_clk_c), .Q(rxdata[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=339, LSE_RLINE=347 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(111[10] 128[24])
    defparam rxdata__i4.GSR = "ENABLED";
    FD1P3IX rxdata__i3 (.D(n15948), .SP(sys_clk_c_enable_47), .CD(n7993), 
            .CK(sys_clk_c), .Q(rxdata[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=339, LSE_RLINE=347 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(111[10] 128[24])
    defparam rxdata__i3.GSR = "ENABLED";
    FD1P3IX rxdata__i2 (.D(n15790), .SP(sys_clk_c_enable_47), .CD(n7993), 
            .CK(sys_clk_c), .Q(rxdata[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=339, LSE_RLINE=347 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(111[10] 128[24])
    defparam rxdata__i2.GSR = "ENABLED";
    FD1P3IX rxdata__i1 (.D(n15787), .SP(sys_clk_c_enable_47), .CD(n7993), 
            .CK(sys_clk_c), .Q(rxdata[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=339, LSE_RLINE=347 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(111[10] 128[24])
    defparam rxdata__i1.GSR = "ENABLED";
    FD1S3IX uart_data__i7 (.D(rxdata[7]), .CK(sys_clk_c), .CD(n16597), 
            .Q(uart_data_R[7])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=339, LSE_RLINE=347 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(137[10] 144[8])
    defparam uart_data__i7.GSR = "ENABLED";
    FD1S3IX uart_data__i6 (.D(rxdata[6]), .CK(sys_clk_c), .CD(n16597), 
            .Q(uart_data_R[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=339, LSE_RLINE=347 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(137[10] 144[8])
    defparam uart_data__i6.GSR = "ENABLED";
    FD1S3IX uart_data__i5 (.D(rxdata[5]), .CK(sys_clk_c), .CD(n16597), 
            .Q(uart_data_R[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=339, LSE_RLINE=347 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(137[10] 144[8])
    defparam uart_data__i5.GSR = "ENABLED";
    FD1S3IX uart_data__i4 (.D(rxdata[4]), .CK(sys_clk_c), .CD(n16597), 
            .Q(uart_data_R[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=339, LSE_RLINE=347 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(137[10] 144[8])
    defparam uart_data__i4.GSR = "ENABLED";
    FD1S3IX uart_data__i3 (.D(rxdata[3]), .CK(sys_clk_c), .CD(n16597), 
            .Q(uart_data_R[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=339, LSE_RLINE=347 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(137[10] 144[8])
    defparam uart_data__i3.GSR = "ENABLED";
    FD1S3IX uart_data__i2 (.D(rxdata[2]), .CK(sys_clk_c), .CD(n16597), 
            .Q(uart_data_R[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=339, LSE_RLINE=347 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(137[10] 144[8])
    defparam uart_data__i2.GSR = "ENABLED";
    FD1S3IX uart_data__i1 (.D(rxdata[1]), .CK(sys_clk_c), .CD(n16597), 
            .Q(uart_data_R[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=339, LSE_RLINE=347 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(137[10] 144[8])
    defparam uart_data__i1.GSR = "ENABLED";
    FD1P3IX rx_cnt_FSM_i1 (.D(n2335[0]), .SP(sys_clk_c_enable_62), .CD(n7993), 
            .CK(sys_clk_c), .Q(n2335[1]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(98[28:41])
    defparam rx_cnt_FSM_i1.GSR = "ENABLED";
    FD1P3IX rx_cnt_FSM_i2 (.D(n2335[1]), .SP(sys_clk_c_enable_62), .CD(n7993), 
            .CK(sys_clk_c), .Q(n2335[2]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(98[28:41])
    defparam rx_cnt_FSM_i2.GSR = "ENABLED";
    FD1P3IX rx_cnt_FSM_i3 (.D(n2335[2]), .SP(sys_clk_c_enable_62), .CD(n7993), 
            .CK(sys_clk_c), .Q(n2335[3]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(98[28:41])
    defparam rx_cnt_FSM_i3.GSR = "ENABLED";
    FD1P3IX rx_cnt_FSM_i4 (.D(n2335[3]), .SP(sys_clk_c_enable_62), .CD(n7993), 
            .CK(sys_clk_c), .Q(n2335[4]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(98[28:41])
    defparam rx_cnt_FSM_i4.GSR = "ENABLED";
    FD1P3IX rx_cnt_FSM_i5 (.D(n2335[4]), .SP(sys_clk_c_enable_62), .CD(n7993), 
            .CK(sys_clk_c), .Q(n2335[5]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(98[28:41])
    defparam rx_cnt_FSM_i5.GSR = "ENABLED";
    FD1P3IX rx_cnt_FSM_i6 (.D(n2335[5]), .SP(sys_clk_c_enable_62), .CD(n7993), 
            .CK(sys_clk_c), .Q(n2335[6]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(98[28:41])
    defparam rx_cnt_FSM_i6.GSR = "ENABLED";
    FD1P3IX rx_cnt_FSM_i7 (.D(n2335[6]), .SP(sys_clk_c_enable_62), .CD(n7993), 
            .CK(sys_clk_c), .Q(n2335[7]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(98[28:41])
    defparam rx_cnt_FSM_i7.GSR = "ENABLED";
    FD1P3IX rx_cnt_FSM_i8 (.D(n2335[7]), .SP(sys_clk_c_enable_62), .CD(n7993), 
            .CK(sys_clk_c), .Q(n2335[8]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(98[28:41])
    defparam rx_cnt_FSM_i8.GSR = "ENABLED";
    FD1P3IX rx_cnt_FSM_i9 (.D(n2335[8]), .SP(sys_clk_c_enable_62), .CD(n7993), 
            .CK(sys_clk_c), .Q(uart_data_7__N_460));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(98[28:41])
    defparam rx_cnt_FSM_i9.GSR = "ENABLED";
    FD1P3IX rx_cnt_FSM_i10 (.D(uart_data_7__N_460), .SP(sys_clk_c_enable_62), 
            .CD(n7993), .CK(sys_clk_c), .Q(n2335[10]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(98[28:41])
    defparam rx_cnt_FSM_i10.GSR = "ENABLED";
    FD1P3IX rx_cnt_FSM_i11 (.D(n2335[10]), .SP(sys_clk_c_enable_62), .CD(n7993), 
            .CK(sys_clk_c), .Q(n2335[11]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(98[28:41])
    defparam rx_cnt_FSM_i11.GSR = "ENABLED";
    FD1P3IX rx_cnt_FSM_i12 (.D(n2335[11]), .SP(sys_clk_c_enable_62), .CD(n7993), 
            .CK(sys_clk_c), .Q(n2335[12]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(98[28:41])
    defparam rx_cnt_FSM_i12.GSR = "ENABLED";
    FD1P3IX rx_cnt_FSM_i13 (.D(n2335[12]), .SP(sys_clk_c_enable_62), .CD(n7993), 
            .CK(sys_clk_c), .Q(n2335[13]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(98[28:41])
    defparam rx_cnt_FSM_i13.GSR = "ENABLED";
    FD1P3IX rx_cnt_FSM_i14 (.D(n2335[13]), .SP(sys_clk_c_enable_62), .CD(n7993), 
            .CK(sys_clk_c), .Q(n2335[14]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(98[28:41])
    defparam rx_cnt_FSM_i14.GSR = "ENABLED";
    FD1P3IX rx_cnt_FSM_i15 (.D(n2335[14]), .SP(sys_clk_c_enable_62), .CD(n7993), 
            .CK(sys_clk_c), .Q(n2335[15]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(98[28:41])
    defparam rx_cnt_FSM_i15.GSR = "ENABLED";
    LUT4 i22206_2_lut (.A(sys_clk_c_enable_62), .B(rx_flag), .Z(n16628)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(101[14] 104[12])
    defparam i22206_2_lut.init = 16'hbbbb;
    FD1S3IX clk_cnt_2268__i1 (.D(n69[1]), .CK(sys_clk_c), .CD(n16628), 
            .Q(clk_cnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268__i1.GSR = "ENABLED";
    FD1S3IX clk_cnt_2268__i2 (.D(n69[2]), .CK(sys_clk_c), .CD(n16628), 
            .Q(clk_cnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268__i2.GSR = "ENABLED";
    FD1S3IX clk_cnt_2268__i3 (.D(n69[3]), .CK(sys_clk_c), .CD(n16628), 
            .Q(clk_cnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268__i3.GSR = "ENABLED";
    FD1S3IX clk_cnt_2268__i4 (.D(n69[4]), .CK(sys_clk_c), .CD(n16628), 
            .Q(clk_cnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268__i4.GSR = "ENABLED";
    FD1S3IX clk_cnt_2268__i5 (.D(n69[5]), .CK(sys_clk_c), .CD(n16628), 
            .Q(clk_cnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268__i5.GSR = "ENABLED";
    FD1S3IX clk_cnt_2268__i6 (.D(n69[6]), .CK(sys_clk_c), .CD(n16628), 
            .Q(clk_cnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268__i6.GSR = "ENABLED";
    FD1S3IX clk_cnt_2268__i7 (.D(n69[7]), .CK(sys_clk_c), .CD(n16628), 
            .Q(clk_cnt[7])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268__i7.GSR = "ENABLED";
    FD1S3IX clk_cnt_2268__i8 (.D(n69[8]), .CK(sys_clk_c), .CD(n16628), 
            .Q(clk_cnt[8])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268__i8.GSR = "ENABLED";
    FD1S3IX clk_cnt_2268__i9 (.D(n69[9]), .CK(sys_clk_c), .CD(n16628), 
            .Q(clk_cnt[9])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268__i9.GSR = "ENABLED";
    FD1S3IX clk_cnt_2268__i10 (.D(n69[10]), .CK(sys_clk_c), .CD(n16628), 
            .Q(clk_cnt[10])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268__i10.GSR = "ENABLED";
    FD1S3IX clk_cnt_2268__i11 (.D(n69[11]), .CK(sys_clk_c), .CD(n16628), 
            .Q(clk_cnt[11])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268__i11.GSR = "ENABLED";
    FD1S3IX clk_cnt_2268__i12 (.D(n69[12]), .CK(sys_clk_c), .CD(n16628), 
            .Q(clk_cnt[12])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268__i12.GSR = "ENABLED";
    FD1S3IX clk_cnt_2268__i13 (.D(n69[13]), .CK(sys_clk_c), .CD(n16628), 
            .Q(clk_cnt[13])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268__i13.GSR = "ENABLED";
    FD1S3IX clk_cnt_2268__i14 (.D(n69[14]), .CK(sys_clk_c), .CD(n16628), 
            .Q(clk_cnt[14])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268__i14.GSR = "ENABLED";
    FD1S3IX clk_cnt_2268__i15 (.D(n69[15]), .CK(sys_clk_c), .CD(n16628), 
            .Q(clk_cnt[15])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268__i15.GSR = "ENABLED";
    LUT4 i1_2_lut_3_lut_4_lut (.A(n2335[5]), .B(n29598), .C(n2335[6]), 
         .D(n2335[8]), .Z(n27755)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_2_lut_3_lut_4_lut.init = 16'hfffe;
    LUT4 i1_2_lut_3_lut_4_lut_adj_239 (.A(n2335[5]), .B(n29598), .C(n2335[7]), 
         .D(n2335[8]), .Z(n27754)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_2_lut_3_lut_4_lut_adj_239.init = 16'hfffe;
    LUT4 i1_2_lut_3_lut_4_lut_adj_240 (.A(n2335[4]), .B(n29597), .C(n2335[3]), 
         .D(n2335[1]), .Z(n27688)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_2_lut_3_lut_4_lut_adj_240.init = 16'hfffe;
    LUT4 i1_2_lut_3_lut_4_lut_adj_241 (.A(n2335[4]), .B(n29597), .C(n2335[2]), 
         .D(n2335[1]), .Z(n27689)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_2_lut_3_lut_4_lut_adj_241.init = 16'hfffe;
    LUT4 i1_2_lut_3_lut_4_lut_adj_242 (.A(n2335[5]), .B(n29636), .C(n29690), 
         .D(n2335[4]), .Z(n27743)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_2_lut_3_lut_4_lut_adj_242.init = 16'hfffe;
    FD1S3IX uart_data__i0 (.D(rxdata[0]), .CK(sys_clk_c), .CD(n16597), 
            .Q(uart_data_R[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=339, LSE_RLINE=347 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(137[10] 144[8])
    defparam uart_data__i0.GSR = "ENABLED";
    LUT4 i1_2_lut_3_lut_4_lut_adj_243 (.A(n2335[4]), .B(n29635), .C(n29689), 
         .D(n2335[5]), .Z(n27692)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_2_lut_3_lut_4_lut_adj_243.init = 16'hfffe;
    LUT4 i2505_1_lut (.A(rx_flag), .Z(n7993)) /* synthesis lut_function=(!(A)) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(75[10] 82[8])
    defparam i2505_1_lut.init = 16'h5555;
    LUT4 i1_4_lut (.A(uart_rxd_d1), .B(rxdata[0]), .C(n2335[1]), .D(n27743), 
         .Z(n15961)) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_4_lut.init = 16'heca0;
    FD1S3IX clk_cnt_2268__i0 (.D(n69[0]), .CK(sys_clk_c), .CD(n16628), 
            .Q(clk_cnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(93[28:42])
    defparam clk_cnt_2268__i0.GSR = "ENABLED";
    LUT4 i1_4_lut_adj_244 (.A(clk_cnt[6]), .B(n27386), .C(n25399), .D(clk_cnt[5]), 
         .Z(sys_clk_c_enable_62)) /* synthesis lut_function=(A (B+(C (D)))+!A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(92[17:38])
    defparam i1_4_lut_adj_244.init = 16'heccc;
    LUT4 i2_4_lut (.A(clk_cnt[4]), .B(clk_cnt[2]), .C(clk_cnt[3]), .D(n4), 
         .Z(n25399)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;
    defparam i2_4_lut.init = 16'hfefa;
    LUT4 i1_2_lut_adj_245 (.A(clk_cnt[0]), .B(clk_cnt[1]), .Z(n4)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_adj_245.init = 16'h8888;
    LUT4 i10448_4_lut (.A(uart_data_7__N_460), .B(rx_flag_N_461), .C(rx_flag), 
         .D(n31), .Z(n16520)) /* synthesis lut_function=(A (B+(C (D)))+!A (B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(75[10] 82[8])
    defparam i10448_4_lut.init = 16'hfcdc;
    LUT4 i1_4_lut_adj_246 (.A(uart_rxd_d1), .B(rxdata[7]), .C(n2335[8]), 
         .D(n27692), .Z(n15798)) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_4_lut_adj_246.init = 16'heca0;
    LUT4 i1_4_lut_adj_247 (.A(uart_rxd_d1), .B(rxdata[6]), .C(n2335[7]), 
         .D(n27755), .Z(n15793)) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_4_lut_adj_247.init = 16'heca0;
    LUT4 i1_4_lut_adj_248 (.A(uart_rxd_d1), .B(rxdata[5]), .C(n2335[6]), 
         .D(n27754), .Z(n15951)) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_4_lut_adj_248.init = 16'heca0;
    LUT4 i1_4_lut_adj_249 (.A(uart_rxd_d1), .B(rxdata[4]), .C(n2335[5]), 
         .D(n27714), .Z(n15945)) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_4_lut_adj_249.init = 16'heca0;
    LUT4 i1_4_lut_adj_250 (.A(uart_rxd_d1), .B(rxdata[3]), .C(n2335[4]), 
         .D(n27704), .Z(n15948)) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_4_lut_adj_250.init = 16'heca0;
    LUT4 i1_4_lut_adj_251 (.A(uart_rxd_d1), .B(rxdata[2]), .C(n2335[3]), 
         .D(n27689), .Z(n15790)) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_4_lut_adj_251.init = 16'heca0;
    LUT4 i1_4_lut_adj_252 (.A(uart_rxd_d1), .B(rxdata[1]), .C(n2335[2]), 
         .D(n27688), .Z(n15787)) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_4_lut_adj_252.init = 16'heca0;
    LUT4 i10523_1_lut (.A(uart_data_7__N_460), .Z(n16597)) /* synthesis lut_function=(!(A)) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(98[28:41])
    defparam i10523_1_lut.init = 16'h5555;
    LUT4 i1_2_lut_3_lut_4_lut_adj_253 (.A(n2335[1]), .B(n29690), .C(n29636), 
         .D(n2335[5]), .Z(n27704)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_2_lut_3_lut_4_lut_adj_253.init = 16'hfffe;
    LUT4 i1_2_lut_rep_299_3_lut_4_lut (.A(n2335[1]), .B(n29690), .C(n2335[5]), 
         .D(n2335[4]), .Z(n29575)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_2_lut_rep_299_3_lut_4_lut.init = 16'hfffe;
    LUT4 i1_2_lut_3_lut_4_lut_adj_254 (.A(n2335[1]), .B(n29690), .C(n29636), 
         .D(n2335[4]), .Z(n27714)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_recv.v(113[13] 123[20])
    defparam i1_2_lut_3_lut_4_lut_adj_254.init = 16'hfffe;
    
endmodule
//
// Verilog Description of module TSALL
// module not written out since it is a black-box. 
//

//
// Verilog Description of module PLL
//

module PLL (sys_clk_c, clk_1us, GND_net) /* synthesis NGD_DRC_MASK=1, syn_module_defined=1 */ ;
    input sys_clk_c;
    output clk_1us;
    input GND_net;
    
    wire sys_clk_c /* synthesis SET_AS_NETWORK=sys_clk_c, is_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(12[19:26])
    wire CLKOP /* synthesis is_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/pll.v(10[17:22])
    wire clk_1us /* synthesis SET_AS_NETWORK=clk_1us, is_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(368[14:21])
    
    EHXPLLJ PLLInst_0 (.CLKI(sys_clk_c), .CLKFB(CLKOP), .PHASESEL0(GND_net), 
            .PHASESEL1(GND_net), .PHASEDIR(GND_net), .PHASESTEP(GND_net), 
            .LOADREG(GND_net), .STDBY(GND_net), .PLLWAKESYNC(GND_net), 
            .RST(GND_net), .RESETC(GND_net), .RESETD(GND_net), .RESETM(GND_net), 
            .ENCLKOP(GND_net), .ENCLKOS(GND_net), .ENCLKOS2(GND_net), 
            .ENCLKOS3(GND_net), .PLLCLK(GND_net), .PLLRST(GND_net), .PLLSTB(GND_net), 
            .PLLWE(GND_net), .PLLDATI0(GND_net), .PLLDATI1(GND_net), .PLLDATI2(GND_net), 
            .PLLDATI3(GND_net), .PLLDATI4(GND_net), .PLLDATI5(GND_net), 
            .PLLDATI6(GND_net), .PLLDATI7(GND_net), .PLLADDR0(GND_net), 
            .PLLADDR1(GND_net), .PLLADDR2(GND_net), .PLLADDR3(GND_net), 
            .PLLADDR4(GND_net), .CLKOP(CLKOP), .CLKOS(clk_1us)) /* synthesis FREQUENCY_PIN_CLKOS="1.000000", FREQUENCY_PIN_CLKOP="120.000000", FREQUENCY_PIN_CLKI="12.000000", ICP_CURRENT="7", LPF_RESISTOR="8", syn_instantiated=1, LSE_LINE_FILE_ID=5, LSE_LCOL=5, LSE_RCOL=2, LSE_LLINE=366, LSE_RLINE=369 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(366[5] 369[2])
    defparam PLLInst_0.CLKI_DIV = 1;
    defparam PLLInst_0.CLKFB_DIV = 10;
    defparam PLLInst_0.CLKOP_DIV = 4;
    defparam PLLInst_0.CLKOS_DIV = 120;
    defparam PLLInst_0.CLKOS2_DIV = 1;
    defparam PLLInst_0.CLKOS3_DIV = 1;
    defparam PLLInst_0.CLKOP_ENABLE = "ENABLED";
    defparam PLLInst_0.CLKOS_ENABLE = "ENABLED";
    defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED";
    defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED";
    defparam PLLInst_0.VCO_BYPASS_A0 = "DISABLED";
    defparam PLLInst_0.VCO_BYPASS_B0 = "DISABLED";
    defparam PLLInst_0.VCO_BYPASS_C0 = "DISABLED";
    defparam PLLInst_0.VCO_BYPASS_D0 = "DISABLED";
    defparam PLLInst_0.CLKOP_CPHASE = 3;
    defparam PLLInst_0.CLKOS_CPHASE = 119;
    defparam PLLInst_0.CLKOS2_CPHASE = 0;
    defparam PLLInst_0.CLKOS3_CPHASE = 0;
    defparam PLLInst_0.CLKOP_FPHASE = 0;
    defparam PLLInst_0.CLKOS_FPHASE = 0;
    defparam PLLInst_0.CLKOS2_FPHASE = 0;
    defparam PLLInst_0.CLKOS3_FPHASE = 0;
    defparam PLLInst_0.FEEDBK_PATH = "CLKOP";
    defparam PLLInst_0.FRACN_ENABLE = "DISABLED";
    defparam PLLInst_0.FRACN_DIV = 0;
    defparam PLLInst_0.CLKOP_TRIM_POL = "RISING";
    defparam PLLInst_0.CLKOP_TRIM_DELAY = 0;
    defparam PLLInst_0.CLKOS_TRIM_POL = "RISING";
    defparam PLLInst_0.CLKOS_TRIM_DELAY = 0;
    defparam PLLInst_0.PLL_USE_WB = "DISABLED";
    defparam PLLInst_0.PREDIVIDER_MUXA1 = 0;
    defparam PLLInst_0.PREDIVIDER_MUXB1 = 1;
    defparam PLLInst_0.PREDIVIDER_MUXC1 = 0;
    defparam PLLInst_0.PREDIVIDER_MUXD1 = 0;
    defparam PLLInst_0.OUTDIVIDER_MUXA2 = "DIVA";
    defparam PLLInst_0.OUTDIVIDER_MUXB2 = "DIVB";
    defparam PLLInst_0.OUTDIVIDER_MUXC2 = "DIVC";
    defparam PLLInst_0.OUTDIVIDER_MUXD2 = "DIVD";
    defparam PLLInst_0.PLL_LOCK_MODE = 0;
    defparam PLLInst_0.STDBY_ENABLE = "DISABLED";
    defparam PLLInst_0.DPHASE_SOURCE = "DISABLED";
    defparam PLLInst_0.PLLRST_ENA = "DISABLED";
    defparam PLLInst_0.MRST_ENA = "DISABLED";
    defparam PLLInst_0.DCRST_ENA = "DISABLED";
    defparam PLLInst_0.DDRST_ENA = "DISABLED";
    defparam PLLInst_0.INTFB_WAKE = "DISABLED";
    
endmodule
//
// Verilog Description of module OLED12832
//

module OLED12832 (sys_clk_c, \cnt_main[0] , char_reg, cnt, n29576, 
            \char_reg[3] , \char_reg[2] , \char_reg[1] , sign, min_h, 
            min_l, OLED_bus_c_4, OLED_bus_c_3, n29583, n29584, n29582, 
            OLED_bus_c_1, n29418, n29564, temp_l, temp_p, temp_h, 
            OLED_bus_c_0, OLED_bus_c_2, n1767, n2523, n1389, n2145, 
            \hour_h[2] , \hour_l[2] , n1011, n4, GND_net, \cnt[1] , 
            \cnt[2] , \cnt[0] , n1013, n1014, n1392, n2148, n1770, 
            n2526, n22, n2054, \hour_h[0] , \hour_l[0] , n28744, 
            n2048, n2147, n2525, n1391, n1769, n1012, n1015, n846, 
            n1393, n1771, \hour_h[3] , \hour_l[3] , n1390, n1768, 
            n2146, n2524, n2149, n2527, n11, n2150, n2528, n2151, 
            n2529, n1017, n1016, n29562, n2052, n22_adj_1, n2053, 
            n28732, n2049, n29563, n1394, n1772, n1395, n1773) /* synthesis syn_module_defined=1 */ ;
    input sys_clk_c;
    output \cnt_main[0] ;
    output [7:0]char_reg;
    output [15:0]cnt;
    output n29576;
    output \char_reg[3] ;
    output \char_reg[2] ;
    output \char_reg[1] ;
    input sign;
    input [3:0]min_h;
    input [3:0]min_l;
    output OLED_bus_c_4;
    output OLED_bus_c_3;
    output n29583;
    output n29584;
    output n29582;
    output OLED_bus_c_1;
    input n29418;
    output n29564;
    input [3:0]temp_l;
    input [3:0]temp_p;
    input [3:0]temp_h;
    output OLED_bus_c_0;
    output OLED_bus_c_2;
    input n1767;
    input n2523;
    input n1389;
    input n2145;
    input \hour_h[2] ;
    input \hour_l[2] ;
    input n1011;
    input n4;
    input GND_net;
    output \cnt[1] ;
    output \cnt[2] ;
    output \cnt[0] ;
    input n1013;
    input n1014;
    input n1392;
    input n2148;
    input n1770;
    input n2526;
    input n22;
    input n2054;
    input \hour_h[0] ;
    input \hour_l[0] ;
    input n28744;
    input n2048;
    input n2147;
    input n2525;
    input n1391;
    input n1769;
    input n1012;
    input n1015;
    output n846;
    input n1393;
    input n1771;
    input \hour_h[3] ;
    input \hour_l[3] ;
    input n1390;
    input n1768;
    input n2146;
    input n2524;
    input n2149;
    input n2527;
    input n11;
    input n2150;
    input n2528;
    input n2151;
    input n2529;
    input n1017;
    input n1016;
    output n29562;
    input n2052;
    input n22_adj_1;
    input n2053;
    input n28732;
    input n2049;
    output n29563;
    input n1394;
    input n1772;
    input n1395;
    input n1773;
    
    wire sys_clk_c /* synthesis SET_AS_NETWORK=sys_clk_c, is_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(12[19:26])
    wire [15:0]num_delay;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(54[13:22])
    wire [15:0]num_delay_15__N_1194;
    
    wire n29554;
    wire [4:0]cnt_main;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(53[12:20])
    
    wire n25220;
    wire [5:0]state_back;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(55[20:30])
    wire [5:0]state_back_5__N_1248;
    
    wire n27451;
    wire [167:0]char;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(51[19:23])
    
    wire sys_clk_c_enable_95, n20524;
    wire [7:0]char_reg_7__N_1166;
    wire [7:0]char_reg_c;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(52[17:25])
    
    wire oled_dcn_N_1613;
    wire [4:0]cnt_init;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(53[22:30])
    
    wire n29638, n27500, n27, n29466, n29465;
    wire [7:0]num;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(52[12:15])
    
    wire n29467, n29560;
    wire [5:0]state;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(55[13:18])
    
    wire n15, n29590, n6, n16, n19, n28063;
    wire [4:0]cnt_write;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(53[42:51])
    
    wire n28161, sys_clk_c_enable_136;
    wire [4:0]n4805;
    
    wire n29664, n28022, n27909, n2130, n2131, n16006, n29703, 
        n27957;
    wire [4:0]cnt_scan;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(53[32:40])
    
    wire n63, n64, n29630, n29665, n29621, sys_clk_c_enable_108, 
        n16671;
    wire [7:0]n37;
    
    wire n29646, n29701, n27792, n27796, n28077, n27794, n29599, 
        n15520, n18, n13, n63_adj_1666, n64_adj_1667, n29453, n29451, 
        n29454, sys_clk_c_enable_100, n27643, n28945, sys_clk_c_enable_83, 
        n30, n11_c, n29594, n29704, n27969, n29712, sys_clk_c_enable_112, 
        n27484, sys_clk_c_enable_135, n28160, n28159, n27662, n64_adj_1668, 
        n29567, n29683, n29685, n12;
    wire [15:0]num_delay_15__N_1505;
    
    wire n20968;
    wire [7:0]x_ph;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(50[17:21])
    
    wire sys_clk_c_enable_14, n29538, n27671, n29666, sys_clk_c_enable_9;
    wire [0:0]n5456;
    
    wire sys_clk_c_enable_10, n27149, n29622, n27520, n30822, n64_adj_1669, 
        n29667, n29588, n15519, n16_adj_1670, n29623, n29449, n29281, 
        n29450, n28764, n11124, n125;
    wire [167:0]n6420;
    
    wire n57, n29423, n29424, n29546, n27638;
    wire [7:0]n1;
    
    wire n29613, n27996, n6_adj_1671, n63_adj_1672, n75, n29670, 
        n4_c, n21080, n2132, n2134, n27626, n25417, n29650, n27_adj_1673, 
        n29420, n29419, n29421, n4_adj_1674, n27497, n30753, n30752, 
        n30755, n29671, n4_adj_1675, n29616, n28941, n29637, n8851, 
        n28048, n27673;
    wire [7:0]x_pl;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(50[23:27])
    
    wire n27670, n29008, n29007, n29555, n38, n29596, n28244, 
        n29737;
    wire [7:0]n4593;
    
    wire n15389, n29589, n29390, n29389, n29391, n29615, n27805;
    wire [7:0]y_p;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(50[12:15])
    
    wire sys_clk_c_enable_15;
    wire [4:0]n2582;
    
    wire n25598, n27632, sys_clk_c_enable_16;
    wire [15:0]n479;
    wire [15:0]n505;
    
    wire n2604, n28944, sys_clk_c_enable_17, n27495, n29387, n29287, 
        n29388, n29647, n6_adj_1676, n6_adj_1677, n29574, n27835, 
        n27994, n28230, n15_adj_1678;
    wire [7:0]n4519;
    
    wire n12_adj_1679, sys_clk_c_enable_125, n14, n36, n11_adj_1680, 
        oled_csn_N_1597, n29626, n29674, n27623, n22754, n29384, 
        n29383, n29385, n23, n29547;
    wire [15:0]cnt_c;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(54[35:38])
    
    wire sys_clk_c_enable_122, n16615, n10, n29673, n29381, n29284, 
        n29382, n29592, n29580, n29591, n19_adj_1681, n6_adj_1682, 
        n42_adj_1683, n21361, n4_adj_1684, sys_clk_c_enable_137, n15_adj_1685, 
        n25086, n44_adj_1686, n27624, n6_adj_1687, n25083, n6_adj_1688, 
        n29625, n28110, n28111, n28112, n28973;
    wire [4:0]n653;
    
    wire n8384, n28117, n28118, n28119, n18_adj_1689, n29679, n29681, 
        n29682, n20949, n28120, n28121, n28122, n9, n27797, n28163, 
        n28164, oled_dat_N_1635, n28170, n28171, n28172, n34, n41, 
        n50, n27602, n23_adj_1690, n8, n27911, sys_clk_c_enable_29, 
        n27067, sys_clk_c_enable_30;
    wire [0:0]n5492;
    
    wire n29691;
    wire [4:0]n443;
    
    wire n30751, n16_adj_1691, n29699, n27642, n28116, n28115, n30750, 
        n19_adj_1692, n20, n24946, n24947, n30756, n24945, n24944, 
        n18_adj_1694, n30782, n30781, n29702, n29037, n30818, n30819, 
        n38_adj_1695, n41_adj_1696, n47, n4_adj_1697, n28763, n29568, 
        n45_adj_1698, n30820, n28106, n28107, n30817, n29277, n29276, 
        n29278, sys_clk_c_enable_123, n16652, n27885, n28193, sys_clk_c_enable_116, 
        n28226, n27907, n29725, n29724;
    wire [15:0]cnt_delay;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(54[24:33])
    
    wire sys_clk_c_enable_131, n16582;
    wire [15:0]n2606;
    
    wire n20_adj_1699, n25871, n32, n20600, n39, n29624, n29728, 
        n13_adj_1700, n39_adj_1701, n29733, n29732, n29736, n29735, 
        n30816, n30821, n29739, n29738, n30783, n6_adj_1702, n6_adj_1703, 
        n5534, n7507, sys_clk_c_enable_38, n29718, n29593, n28108, 
        n28109, n19_adj_1704, n21, n28169, n28168, n19_adj_1705, 
        n19_adj_1706, n24994, sys_clk_c_enable_121, n16617, n11_adj_1707, 
        n29707, n16_adj_1708, n12995, n7769, n29520, n4_adj_1709, 
        n29523, n29611, n28167, n15356, n29651, n4_adj_1710, n28166, 
        n6_adj_1711, sys_clk_c_enable_92, n29719, n6_adj_1712, n13_adj_1713, 
        n29653, n1868, n28124, n28123, n15598, n644;
    wire [4:0]cnt_scan_4__N_1271;
    
    wire n27977, n22719, n24993, n24992, n8312, n29711, n57_adj_1714;
    wire [4:0]n2;
    
    wire n24991, n16_adj_1716, n16601, n27371, n28162, n24990, n28113, 
        n28114, n11_adj_1717, n27493, n24989, n36_adj_1718, n29608, 
        n29705, sys_clk_c_enable_106, n16634, n24988, n28258, n18_adj_1719, 
        n29142, n29141, n29717, n24987, n27668, n27667, n29521, 
        n24959, n24958, n29581, n6_adj_1720, n6_adj_1721, n6_adj_1722, 
        n29452, n17, n6_adj_1723, n9_adj_1724, n4_adj_1725, n12_adj_1726, 
        n28125, n57_adj_1727, n61, n2796, n12_adj_1728, n27590, 
        n24, n27_adj_1729, n29425, n12_adj_1730, n27527, n27407, 
        n29632, n28696, n29386, n12_adj_1731, n24957, n16530, n27589, 
        n12_adj_1732, n29392, n12_adj_1733, n12_adj_1734, n24956, 
        n27_adj_1735, n12_adj_1736, n12_adj_1737, n29726, n27592, 
        n12_adj_1738, n24_adj_1739, n27591, n21163, n27472, n15_adj_1740, 
        n29652, n16_adj_1741, n29740, n16_adj_1742, n24955, n16_adj_1744, 
        n24954, n27411, n16_adj_1745, n24_adj_1746, n28943, n5, 
        n28720, n28249, n45_adj_1747, n47_adj_1748;
    wire [5:0]state_5__N_1553;
    
    wire n24_adj_1749, n27524, n15_adj_1750, n16_adj_1751, n14962, 
        n24_adj_1752, n24_adj_1753, n16_adj_1754, n16_adj_1755, n24_adj_1756, 
        n24_adj_1757, n24_adj_1760, n24_adj_1761, n50_adj_1762, n24_adj_1763, 
        n12_adj_1764, n6_adj_1765, n24_adj_1766, n24_adj_1767, n6_adj_1768, 
        n24_adj_1769, n6_adj_1770, n24_adj_1771, n4_adj_1772, n16_adj_1773, 
        n24953, n15556, n35, n31, n29734, n28194, n24952, n25031;
    wire [5:0]state_back_5__N_1583;
    
    wire n24_adj_1775, n25030, n16_adj_1776, n27611, n16_adj_1777, 
        n25029, n16_adj_1778, n25028, n24951, n4_adj_1779, n16_adj_1780, 
        n29333, n29334, n29348, n29570, n16_adj_1782, n29349, n16_adj_1783, 
        n24950, n16_adj_1784, n24949, n24948;
    
    FD1S3AX num_delay_i15 (.D(num_delay_15__N_1194[15]), .CK(sys_clk_c), 
            .Q(num_delay[15])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam num_delay_i15.GSR = "ENABLED";
    FD1S3AX num_delay_i14 (.D(num_delay_15__N_1194[14]), .CK(sys_clk_c), 
            .Q(num_delay[14])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam num_delay_i14.GSR = "ENABLED";
    FD1S3AX num_delay_i13 (.D(num_delay_15__N_1194[13]), .CK(sys_clk_c), 
            .Q(num_delay[13])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam num_delay_i13.GSR = "ENABLED";
    FD1S3AX num_delay_i12 (.D(num_delay_15__N_1194[12]), .CK(sys_clk_c), 
            .Q(num_delay[12])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam num_delay_i12.GSR = "ENABLED";
    FD1S3AX num_delay_i11 (.D(num_delay_15__N_1194[11]), .CK(sys_clk_c), 
            .Q(num_delay[11])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam num_delay_i11.GSR = "ENABLED";
    FD1S3AX num_delay_i10 (.D(num_delay_15__N_1194[10]), .CK(sys_clk_c), 
            .Q(num_delay[10])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam num_delay_i10.GSR = "ENABLED";
    FD1S3AX num_delay_i9 (.D(num_delay_15__N_1194[9]), .CK(sys_clk_c), .Q(num_delay[9])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam num_delay_i9.GSR = "ENABLED";
    FD1S3AX num_delay_i8 (.D(num_delay_15__N_1194[8]), .CK(sys_clk_c), .Q(num_delay[8])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam num_delay_i8.GSR = "ENABLED";
    FD1S3AX num_delay_i7 (.D(num_delay_15__N_1194[7]), .CK(sys_clk_c), .Q(num_delay[7])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam num_delay_i7.GSR = "ENABLED";
    FD1S3AX num_delay_i6 (.D(num_delay_15__N_1194[6]), .CK(sys_clk_c), .Q(num_delay[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam num_delay_i6.GSR = "ENABLED";
    LUT4 i1_2_lut_4_lut (.A(n29554), .B(cnt_main[1]), .C(cnt_main[4]), 
         .D(cnt_main[3]), .Z(n25220)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam i1_2_lut_4_lut.init = 16'h0008;
    FD1S3AX num_delay_i5 (.D(num_delay_15__N_1194[5]), .CK(sys_clk_c), .Q(num_delay[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam num_delay_i5.GSR = "ENABLED";
    FD1S3AX num_delay_i4 (.D(num_delay_15__N_1194[4]), .CK(sys_clk_c), .Q(num_delay[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam num_delay_i4.GSR = "ENABLED";
    FD1S3AX num_delay_i3 (.D(num_delay_15__N_1194[3]), .CK(sys_clk_c), .Q(num_delay[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam num_delay_i3.GSR = "ENABLED";
    FD1S3AY num_delay_i2 (.D(num_delay_15__N_1194[2]), .CK(sys_clk_c), .Q(num_delay[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam num_delay_i2.GSR = "ENABLED";
    FD1S3AX num_delay_i1 (.D(num_delay_15__N_1194[1]), .CK(sys_clk_c), .Q(num_delay[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam num_delay_i1.GSR = "ENABLED";
    FD1S3AX state_back_i5 (.D(state_back_5__N_1248[5]), .CK(sys_clk_c), 
            .Q(state_back[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam state_back_i5.GSR = "ENABLED";
    LUT4 i1_2_lut_4_lut_adj_48 (.A(n29554), .B(cnt_main[1]), .C(cnt_main[4]), 
         .D(\cnt_main[0] ), .Z(n27451)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam i1_2_lut_4_lut_adj_48.init = 16'h0800;
    FD1S3AX state_back_i4 (.D(state_back_5__N_1248[4]), .CK(sys_clk_c), 
            .Q(state_back[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam state_back_i4.GSR = "ENABLED";
    FD1S3AX state_back_i3 (.D(state_back_5__N_1248[3]), .CK(sys_clk_c), 
            .Q(state_back[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam state_back_i3.GSR = "ENABLED";
    FD1S3AX state_back_i2 (.D(state_back_5__N_1248[2]), .CK(sys_clk_c), 
            .Q(state_back[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam state_back_i2.GSR = "ENABLED";
    FD1S3AX state_back_i1 (.D(state_back_5__N_1248[1]), .CK(sys_clk_c), 
            .Q(state_back[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam state_back_i1.GSR = "ENABLED";
    FD1P3IX char_i0_i6 (.D(n25220), .SP(sys_clk_c_enable_95), .CD(n20524), 
            .CK(sys_clk_c), .Q(char[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam char_i0_i6.GSR = "ENABLED";
    FD1S3AX char_reg_i7 (.D(char_reg_7__N_1166[7]), .CK(sys_clk_c), .Q(char_reg[7])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam char_reg_i7.GSR = "ENABLED";
    FD1S3AX char_reg_i6 (.D(char_reg_7__N_1166[6]), .CK(sys_clk_c), .Q(char_reg[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam char_reg_i6.GSR = "ENABLED";
    FD1S3AX char_reg_i5 (.D(char_reg_7__N_1166[5]), .CK(sys_clk_c), .Q(char_reg_c[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam char_reg_i5.GSR = "ENABLED";
    LUT4 i1_4_lut_4_lut (.A(oled_dcn_N_1613), .B(cnt_init[0]), .C(n29638), 
         .D(n27500), .Z(n27)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (B (D)+!B ((D)+!C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[7] 124[14])
    defparam i1_4_lut_4_lut.init = 16'hfd01;
    PFUMX i22756 (.BLUT(n29466), .ALUT(n29465), .C0(num[2]), .Z(n29467));
    LUT4 i21918_2_lut_rep_284_4_lut (.A(oled_dcn_N_1613), .B(cnt_init[0]), 
         .C(n29638), .D(cnt[4]), .Z(n29560)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[7] 124[14])
    defparam i21918_2_lut_rep_284_4_lut.init = 16'h0001;
    LUT4 i1_4_lut (.A(state[1]), .B(n15), .C(n29590), .D(cnt_main[4]), 
         .Z(n6)) /* synthesis lut_function=(!((B (C (D))+!B (C+!(D)))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i1_4_lut.init = 16'h0a88;
    LUT4 i1_4_lut_adj_49 (.A(state[0]), .B(num_delay[12]), .C(n16), .D(n19), 
         .Z(num_delay_15__N_1194[12])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_49.init = 16'hdc50;
    FD1S3AX char_reg_i4 (.D(char_reg_7__N_1166[4]), .CK(sys_clk_c), .Q(char_reg_c[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam char_reg_i4.GSR = "ENABLED";
    LUT4 i21912_3_lut (.A(n29576), .B(cnt[4]), .C(cnt[3]), .Z(n28063)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(117[20] 120[14])
    defparam i21912_3_lut.init = 16'h1010;
    LUT4 i22010_3_lut (.A(\char_reg[3] ), .B(\char_reg[2] ), .C(cnt_write[1]), 
         .Z(n28161)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i22010_3_lut.init = 16'hcaca;
    FD1S3AX char_reg_i3 (.D(char_reg_7__N_1166[3]), .CK(sys_clk_c), .Q(\char_reg[3] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam char_reg_i3.GSR = "ENABLED";
    FD1S3AX char_reg_i2 (.D(char_reg_7__N_1166[2]), .CK(sys_clk_c), .Q(\char_reg[2] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam char_reg_i2.GSR = "ENABLED";
    FD1S3AX char_reg_i1 (.D(char_reg_7__N_1166[1]), .CK(sys_clk_c), .Q(\char_reg[1] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam char_reg_i1.GSR = "ENABLED";
    FD1P3AX cnt_main_i0_i3 (.D(n4805[3]), .SP(sys_clk_c_enable_136), .CK(sys_clk_c), 
            .Q(cnt_main[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_main_i0_i3.GSR = "ENABLED";
    LUT4 i21775_2_lut_rep_388 (.A(\cnt_main[0] ), .B(cnt_main[1]), .Z(n29664)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i21775_2_lut_rep_388.init = 16'heeee;
    LUT4 i36_3_lut_3_lut_4_lut (.A(\cnt_main[0] ), .B(cnt_main[1]), .C(cnt_main[3]), 
         .D(sign), .Z(n28022)) /* synthesis lut_function=(A+(B+(C (D)))) */ ;
    defparam i36_3_lut_3_lut_4_lut.init = 16'hfeee;
    LUT4 i21764_2_lut_3_lut (.A(\cnt_main[0] ), .B(cnt_main[1]), .C(cnt_main[2]), 
         .Z(n27909)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i21764_2_lut_3_lut.init = 16'hfefe;
    LUT4 i9940_2_lut (.A(n2130), .B(n2131), .Z(n16006)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[51:79])
    defparam i9940_2_lut.init = 16'heeee;
    LUT4 i21810_3_lut_4_lut (.A(\cnt_main[0] ), .B(cnt_main[1]), .C(n29703), 
         .D(cnt_main[2]), .Z(n27957)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i21810_3_lut_4_lut.init = 16'hfffe;
    LUT4 i1_2_lut (.A(cnt_scan[4]), .B(n63), .Z(n64)) /* synthesis lut_function=(!(A+!(B))) */ ;
    defparam i1_2_lut.init = 16'h4444;
    LUT4 mux_19_Mux_125_i7_3_lut_rep_354_4_lut_3_lut (.A(\cnt_main[0] ), .B(cnt_main[1]), 
         .C(cnt_main[2]), .Z(n29630)) /* synthesis lut_function=(!(A (B (C))+!A !(B+(C)))) */ ;
    defparam mux_19_Mux_125_i7_3_lut_rep_354_4_lut_3_lut.init = 16'h7e7e;
    LUT4 i22204_2_lut_rep_389 (.A(state[1]), .B(state[2]), .Z(n29665)) /* synthesis lut_function=(!(A+(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i22204_2_lut_rep_389.init = 16'h1111;
    LUT4 equal_1322_i8_2_lut_rep_345_3_lut (.A(state[1]), .B(state[2]), 
         .C(state[0]), .Z(n29621)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam equal_1322_i8_2_lut_rep_345_3_lut.init = 16'hfefe;
    FD1P3IX num_2277__i5 (.D(n37[5]), .SP(sys_clk_c_enable_108), .CD(n16671), 
            .CK(sys_clk_c), .Q(num[5])) /* synthesis syn_use_carry_chain=1 */ ;
    defparam num_2277__i5.GSR = "ENABLED";
    LUT4 i21662_2_lut_4_lut (.A(n29646), .B(n29701), .C(oled_dcn_N_1613), 
         .D(state_back[5]), .Z(n27792)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (B (D))) */ ;
    defparam i21662_2_lut_4_lut.init = 16'hec00;
    LUT4 i21664_2_lut_4_lut (.A(n29646), .B(n29701), .C(oled_dcn_N_1613), 
         .D(state_back[0]), .Z(n27796)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (B (D))) */ ;
    defparam i21664_2_lut_4_lut.init = 16'hec00;
    LUT4 i21926_3_lut (.A(n29576), .B(cnt[4]), .C(cnt[3]), .Z(n28077)) /* synthesis lut_function=(!(A+((C)+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(117[20] 120[14])
    defparam i21926_3_lut.init = 16'h0404;
    LUT4 i21663_2_lut_4_lut (.A(n29646), .B(n29701), .C(oled_dcn_N_1613), 
         .D(state_back[4]), .Z(n27794)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (B (D))) */ ;
    defparam i21663_2_lut_4_lut.init = 16'hec00;
    LUT4 i1_4_lut_adj_50 (.A(state[2]), .B(n29599), .C(n15520), .D(state[1]), 
         .Z(n18)) /* synthesis lut_function=(A (B (C+(D))+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i1_4_lut_adj_50.init = 16'ha8a0;
    LUT4 i2_3_lut_4_lut (.A(state[1]), .B(state[2]), .C(state_back[4]), 
         .D(state[5]), .Z(n13)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i2_3_lut_4_lut.init = 16'h1000;
    LUT4 i1_2_lut_adj_51 (.A(cnt_scan[4]), .B(n63_adj_1666), .Z(n64_adj_1667)) /* synthesis lut_function=(!(A+!(B))) */ ;
    defparam i1_2_lut_adj_51.init = 16'h4444;
    PFUMX i22748 (.BLUT(n29453), .ALUT(n29451), .C0(cnt_scan[3]), .Z(n29454));
    FD1P3AX cnt_init_i0_i0 (.D(n27643), .SP(sys_clk_c_enable_100), .CK(sys_clk_c), 
            .Q(cnt_init[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_init_i0_i0.GSR = "ENABLED";
    LUT4 n28945_bdd_2_lut_3_lut_4_lut (.A(state[1]), .B(state[2]), .C(n28945), 
         .D(state[0]), .Z(sys_clk_c_enable_83)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam n28945_bdd_2_lut_3_lut_4_lut.init = 16'hfffe;
    LUT4 i2_2_lut_3_lut (.A(state[1]), .B(state[2]), .C(state_back[3]), 
         .Z(n30)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i2_2_lut_3_lut.init = 16'h1010;
    LUT4 i1_2_lut_3_lut (.A(state[1]), .B(state[2]), .C(state_back[2]), 
         .Z(n11_c)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i1_2_lut_3_lut.init = 16'h1010;
    LUT4 i22190_4_lut_4_lut (.A(n29594), .B(n29704), .C(n27969), .D(n29712), 
         .Z(sys_clk_c_enable_112)) /* synthesis lut_function=(!(A+(B (D)+!B ((D)+!C)))) */ ;
    defparam i22190_4_lut_4_lut.init = 16'h0054;
    LUT4 i22265_3_lut_4_lut_4_lut (.A(state[1]), .B(state[2]), .C(n27484), 
         .D(state[0]), .Z(sys_clk_c_enable_135)) /* synthesis lut_function=(!(A (B+(C))+!A (B+(C+!(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i22265_3_lut_4_lut_4_lut.init = 16'h0302;
    LUT4 i22009_3_lut (.A(char_reg_c[5]), .B(char_reg_c[4]), .C(cnt_write[1]), 
         .Z(n28160)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i22009_3_lut.init = 16'hcaca;
    LUT4 i22008_3_lut (.A(char_reg[7]), .B(char_reg[6]), .C(cnt_write[1]), 
         .Z(n28159)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i22008_3_lut.init = 16'hcaca;
    FD1P3AX char_i0_i123 (.D(n27662), .SP(sys_clk_c_enable_95), .CK(sys_clk_c), 
            .Q(char[123])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam char_i0_i123.GSR = "ENABLED";
    LUT4 i1_2_lut_adj_52 (.A(cnt_scan[4]), .B(n29454), .Z(n64_adj_1668)) /* synthesis lut_function=(!(A+!(B))) */ ;
    defparam i1_2_lut_adj_52.init = 16'h4444;
    LUT4 i2_3_lut_4_lut_adj_53 (.A(cnt_main[2]), .B(n29567), .C(n29683), 
         .D(n29685), .Z(n27662)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam i2_3_lut_4_lut_adj_53.init = 16'h8000;
    LUT4 mux_19_Mux_1_i12_3_lut (.A(min_h[1]), .B(min_l[1]), .C(\cnt_main[0] ), 
         .Z(n12)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam mux_19_Mux_1_i12_3_lut.init = 16'hcaca;
    LUT4 i33_4_lut (.A(num_delay[12]), .B(num_delay_15__N_1505[12]), .C(state[2]), 
         .D(n20968), .Z(n16)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut.init = 16'h0aca;
    FD1P3AX x_ph_i0_i0 (.D(n29538), .SP(sys_clk_c_enable_14), .CK(sys_clk_c), 
            .Q(x_ph[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam x_ph_i0_i0.GSR = "ENABLED";
    FD1P3AX char_i0_i0 (.D(n27671), .SP(sys_clk_c_enable_14), .CK(sys_clk_c), 
            .Q(char[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam char_i0_i0.GSR = "ENABLED";
    LUT4 i2177_2_lut_rep_390 (.A(state[1]), .B(state[0]), .Z(n29666)) /* synthesis lut_function=(A (B)) */ ;
    defparam i2177_2_lut_rep_390.init = 16'h8888;
    FD1S3AX char_reg_i0 (.D(char_reg_7__N_1166[0]), .CK(sys_clk_c), .Q(char_reg_c[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam char_reg_i0.GSR = "ENABLED";
    FD1P3AY oled_csn_302 (.D(n5456[0]), .SP(sys_clk_c_enable_9), .CK(sys_clk_c), 
            .Q(OLED_bus_c_4)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam oled_csn_302.GSR = "ENABLED";
    FD1P3AX oled_dcn_304 (.D(n27149), .SP(sys_clk_c_enable_10), .CK(sys_clk_c), 
            .Q(OLED_bus_c_3)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam oled_dcn_304.GSR = "ENABLED";
    FD1S3AY state_back_i0 (.D(state_back_5__N_1248[0]), .CK(sys_clk_c), 
            .Q(state_back[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam state_back_i0.GSR = "ENABLED";
    FD1S3AY num_delay_i0 (.D(num_delay_15__N_1194[0]), .CK(sys_clk_c), .Q(num_delay[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam num_delay_i0.GSR = "ENABLED";
    LUT4 i2_4_lut_4_lut (.A(state[1]), .B(state[0]), .C(n29622), .D(n27520), 
         .Z(n27484)) /* synthesis lut_function=(A (B+(C+(D)))+!A (B (C)+!B (C+(D)))) */ ;
    defparam i2_4_lut_4_lut.init = 16'hfbf8;
    LUT4 i1_2_lut_adj_54 (.A(cnt_scan[4]), .B(n30822), .Z(n64_adj_1669)) /* synthesis lut_function=(!(A+!(B))) */ ;
    defparam i1_2_lut_adj_54.init = 16'h4444;
    LUT4 i1_2_lut_rep_391 (.A(cnt_main[2]), .B(cnt_main[1]), .Z(n29667)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam i1_2_lut_rep_391.init = 16'heeee;
    LUT4 i1_2_lut_rep_312_3_lut_4_lut (.A(cnt_main[2]), .B(cnt_main[1]), 
         .C(sign), .D(\cnt_main[0] ), .Z(n29588)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam i1_2_lut_rep_312_3_lut_4_lut.init = 16'hfffe;
    LUT4 i2_3_lut_4_lut_adj_55 (.A(cnt_main[2]), .B(cnt_main[1]), .C(cnt_main[3]), 
         .D(\cnt_main[0] ), .Z(n29590)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam i2_3_lut_4_lut_adj_55.init = 16'hfffe;
    LUT4 i1_4_lut_adj_56 (.A(cnt_init[0]), .B(n15519), .C(state_back[2]), 
         .D(n29701), .Z(n16_adj_1670)) /* synthesis lut_function=(!(A+!(B+(C (D))))) */ ;
    defparam i1_4_lut_adj_56.init = 16'h5444;
    LUT4 i1_3_lut (.A(state_back[2]), .B(n29646), .C(oled_dcn_N_1613), 
         .Z(n15519)) /* synthesis lut_function=(A (B)+!A !((C)+!B)) */ ;
    defparam i1_3_lut.init = 16'h8c8c;
    LUT4 i22239_2_lut_rep_347_3_lut (.A(cnt_main[2]), .B(cnt_main[1]), .C(\cnt_main[0] ), 
         .Z(n29623)) /* synthesis lut_function=(!(A+(B+(C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam i22239_2_lut_rep_347_3_lut.init = 16'h0101;
    PFUMX i22745 (.BLUT(n29449), .ALUT(n29281), .C0(cnt_scan[1]), .Z(n29450));
    LUT4 mux_562_Mux_23_i125_4_lut (.A(n28764), .B(n11124), .C(n29583), 
         .D(n29584), .Z(n125)) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[51:79])
    defparam mux_562_Mux_23_i125_4_lut.init = 16'h3a0a;
    FD1P3AX char_i0_i53 (.D(n6420[53]), .SP(sys_clk_c_enable_95), .CK(sys_clk_c), 
            .Q(char[53])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam char_i0_i53.GSR = "ENABLED";
    PFUMX i22731 (.BLUT(n57), .ALUT(n29423), .C0(cnt_scan[3]), .Z(n29424));
    LUT4 i2_3_lut_rep_270_4_lut (.A(n29567), .B(cnt_main[4]), .C(cnt_main[1]), 
         .D(cnt_main[3]), .Z(n29546)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ;
    defparam i2_3_lut_rep_270_4_lut.init = 16'hfffd;
    LUT4 num_2277_mux_6_i2_3_lut_4_lut (.A(n29590), .B(n27638), .C(state[3]), 
         .D(n37[1]), .Z(n1[1])) /* synthesis lut_function=(A (C (D))+!A (B ((D)+!C)+!B (C (D)))) */ ;
    defparam num_2277_mux_6_i2_3_lut_4_lut.init = 16'hf404;
    LUT4 i15129_4_lut (.A(n29613), .B(n27996), .C(num[4]), .D(n6_adj_1671), 
         .Z(n63_adj_1672)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;
    defparam i15129_4_lut.init = 16'h0004;
    LUT4 i22211_2_lut_3_lut (.A(n29567), .B(cnt_main[4]), .C(\cnt_main[0] ), 
         .Z(n75)) /* synthesis lut_function=(!((B+(C))+!A)) */ ;
    defparam i22211_2_lut_3_lut.init = 16'h0202;
    LUT4 i1_2_lut_rep_394 (.A(cnt_scan[1]), .B(cnt_scan[2]), .Z(n29670)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam i1_2_lut_rep_394.init = 16'h2222;
    LUT4 i15041_4_lut (.A(cnt_init[2]), .B(cnt_init[1]), .C(oled_dcn_N_1613), 
         .D(n4_c), .Z(n21080)) /* synthesis lut_function=(A (B+(C (D)))) */ ;
    defparam i15041_4_lut.init = 16'ha888;
    LUT4 i21848_3_lut (.A(n2132), .B(n2131), .C(n2134), .Z(n27996)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i21848_3_lut.init = 16'h8080;
    LUT4 i1_2_lut_3_lut_adj_57 (.A(cnt_scan[1]), .B(cnt_scan[2]), .C(cnt_scan[0]), 
         .Z(n27626)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;
    defparam i1_2_lut_3_lut_adj_57.init = 16'h2020;
    LUT4 i15112_4_lut (.A(state[2]), .B(cnt_scan[4]), .C(n25417), .D(n29650), 
         .Z(n27_adj_1673)) /* synthesis lut_function=(!(A+(B+(C (D))))) */ ;
    defparam i15112_4_lut.init = 16'h0111;
    PFUMX i22729 (.BLUT(n29420), .ALUT(n29419), .C0(n29582), .Z(n29421));
    LUT4 i2_4_lut (.A(n29599), .B(n4_adj_1674), .C(n21080), .D(state[0]), 
         .Z(n27497)) /* synthesis lut_function=(!(A ((C+(D))+!B)+!A ((C)+!B))) */ ;
    defparam i2_4_lut.init = 16'h040c;
    LUT4 n30754_bdd_3_lut_4_lut (.A(n30753), .B(cnt_scan[2]), .C(cnt_scan[0]), 
         .D(n30752), .Z(n30755)) /* synthesis lut_function=(A (B (C (D))+!B ((D)+!C))+!A (C (D))) */ ;
    defparam n30754_bdd_3_lut_4_lut.init = 16'hf202;
    LUT4 num_2277_mux_6_i3_3_lut_4_lut (.A(n29590), .B(n27638), .C(state[3]), 
         .D(n37[2]), .Z(n1[2])) /* synthesis lut_function=(A (C (D))+!A (B ((D)+!C)+!B (C (D)))) */ ;
    defparam num_2277_mux_6_i3_3_lut_4_lut.init = 16'hf404;
    FD1P3AX char_i0_i13 (.D(n6420[21]), .SP(sys_clk_c_enable_95), .CK(sys_clk_c), 
            .Q(char[13])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam char_i0_i13.GSR = "ENABLED";
    LUT4 i14398_2_lut_rep_395 (.A(state[1]), .B(state[0]), .Z(n29671)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i14398_2_lut_rep_395.init = 16'heeee;
    LUT4 num_2277_mux_6_i1_4_lut (.A(state[0]), .B(n37[0]), .C(state[3]), 
         .D(n4_adj_1675), .Z(n1[0])) /* synthesis lut_function=(A (B (C))+!A (B (C+(D))+!B !(C+!(D)))) */ ;
    defparam num_2277_mux_6_i1_4_lut.init = 16'hc5c0;
    LUT4 i1_4_lut_adj_58 (.A(n29616), .B(cnt_main[4]), .C(n29588), .D(cnt_main[3]), 
         .Z(n4_adj_1675)) /* synthesis lut_function=(!(A (B+!(C+!(D)))+!A (B+!(C (D))))) */ ;
    defparam i1_4_lut_adj_58.init = 16'h3022;
    LUT4 n27625_bdd_4_lut_22588 (.A(n29712), .B(cnt_scan[4]), .C(cnt_scan[0]), 
         .D(cnt_scan[3]), .Z(n28941)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ;
    defparam n27625_bdd_4_lut_22588.init = 16'hffef;
    LUT4 i1_2_lut_rep_361_3_lut (.A(state[1]), .B(state[0]), .C(state[2]), 
         .Z(n29637)) /* synthesis lut_function=(A+(B+!(C))) */ ;
    defparam i1_2_lut_rep_361_3_lut.init = 16'hefef;
    LUT4 i2157_2_lut_2_lut_3_lut_3_lut_3_lut (.A(state[1]), .B(state[0]), 
         .C(state[2]), .Z(n8851)) /* synthesis lut_function=(A+(B (C))) */ ;
    defparam i2157_2_lut_2_lut_3_lut_3_lut_3_lut.init = 16'heaea;
    LUT4 i22275_2_lut (.A(cnt_scan[3]), .B(cnt_scan[1]), .Z(n28048)) /* synthesis lut_function=(A+!(B)) */ ;
    defparam i22275_2_lut.init = 16'hbbbb;
    FD1P3AX char_i0_i1 (.D(n27673), .SP(sys_clk_c_enable_14), .CK(sys_clk_c), 
            .Q(char[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam char_i0_i1.GSR = "ENABLED";
    FD1P3AX x_pl_i0_i3 (.D(n27670), .SP(sys_clk_c_enable_14), .CK(sys_clk_c), 
            .Q(x_pl[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam x_pl_i0_i3.GSR = "ENABLED";
    LUT4 i1_4_lut_adj_59 (.A(cnt_init[0]), .B(n29646), .C(state[1]), .D(oled_dcn_N_1613), 
         .Z(n15520)) /* synthesis lut_function=(A (B)+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[7] 124[14])
    defparam i1_4_lut_adj_59.init = 16'hc888;
    LUT4 n29008_bdd_4_lut (.A(n29008), .B(n29007), .C(\cnt_main[0] ), 
         .D(n29555), .Z(n29538)) /* synthesis lut_function=(!(A (B (D)+!B (C+(D)))+!A (((D)+!C)+!B))) */ ;
    defparam n29008_bdd_4_lut.init = 16'h00ca;
    LUT4 i1_2_lut_rep_320_3_lut_4_lut (.A(state[1]), .B(state[0]), .C(n38), 
         .D(n29712), .Z(n29596)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;
    defparam i1_2_lut_rep_320_3_lut_4_lut.init = 16'h0010;
    LUT4 i22178_4_lut (.A(n29567), .B(n27957), .C(n29590), .D(cnt_main[4]), 
         .Z(n28244)) /* synthesis lut_function=(!(A (B (C (D))+!B (C+!(D))))) */ ;
    defparam i22178_4_lut.init = 16'h5fdd;
    LUT4 i14783_3_lut (.A(n29737), .B(n29567), .C(cnt_main[4]), .Z(n4593[1])) /* synthesis lut_function=(A (B)+!A (B (C))) */ ;
    defparam i14783_3_lut.init = 16'hc8c8;
    LUT4 i2_4_lut_4_lut_adj_60 (.A(num[4]), .B(n29613), .C(n16006), .D(n2132), 
         .Z(n15389)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[59:71])
    defparam i2_4_lut_4_lut_adj_60.init = 16'hfffb;
    LUT4 i21723_2_lut_rep_313_3_lut_4_lut (.A(state[4]), .B(state[5]), .C(state[2]), 
         .D(state[3]), .Z(n29589)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(67[5:9])
    defparam i21723_2_lut_rep_313_3_lut_4_lut.init = 16'hfffe;
    PFUMX i22710 (.BLUT(n29390), .ALUT(n29389), .C0(cnt_scan[3]), .Z(n29391));
    LUT4 i21673_2_lut_3_lut (.A(char[0]), .B(n29615), .C(n15389), .Z(n27805)) /* synthesis lut_function=(A ((C)+!B)+!A (C)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[59:71])
    defparam i21673_2_lut_3_lut.init = 16'hf2f2;
    FD1P3AX y_p_i0_i4 (.D(n29567), .SP(sys_clk_c_enable_15), .CK(sys_clk_c), 
            .Q(y_p[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam y_p_i0_i4.GSR = "ENABLED";
    LUT4 i2925_2_lut (.A(cnt_write[1]), .B(cnt_write[0]), .Z(n2582[1])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(152[25:41])
    defparam i2925_2_lut.init = 16'h6666;
    LUT4 i2_3_lut_4_lut_4_lut (.A(char[0]), .B(n29615), .C(n25598), .D(char[6]), 
         .Z(n27632)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[59:71])
    defparam i2_3_lut_4_lut_4_lut.init = 16'h2000;
    FD1P3AX num_2277__i4 (.D(n1[4]), .SP(sys_clk_c_enable_16), .CK(sys_clk_c), 
            .Q(num[4])) /* synthesis syn_use_carry_chain=1 */ ;
    defparam num_2277__i4.GSR = "ENABLED";
    LUT4 i14420_2_lut (.A(n479[0]), .B(oled_dcn_N_1613), .Z(n505[0])) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam i14420_2_lut.init = 16'h2222;
    LUT4 i1_2_lut_3_lut_adj_61 (.A(char[0]), .B(n29615), .C(n2130), .Z(n6_adj_1671)) /* synthesis lut_function=(A ((C)+!B)+!A (C)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[59:71])
    defparam i1_2_lut_3_lut_adj_61.init = 16'hf2f2;
    LUT4 n2604_bdd_3_lut_22590 (.A(n2604), .B(state[4]), .C(state[5]), 
         .Z(n28944)) /* synthesis lut_function=(A+(B+!(C))) */ ;
    defparam n2604_bdd_3_lut_22590.init = 16'hefef;
    FD1P3AX oled_dat_306 (.D(n27495), .SP(sys_clk_c_enable_17), .CK(sys_clk_c), 
            .Q(OLED_bus_c_1)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam oled_dat_306.GSR = "ENABLED";
    PFUMX i22707 (.BLUT(n29387), .ALUT(n29287), .C0(cnt_scan[1]), .Z(n29388));
    LUT4 i1_4_lut_adj_62 (.A(state[2]), .B(state_back[3]), .C(n29647), 
         .D(n6_adj_1676), .Z(n6_adj_1677)) /* synthesis lut_function=(A (B (C+(D)))) */ ;
    defparam i1_4_lut_adj_62.init = 16'h8880;
    LUT4 i22164_4_lut (.A(n29567), .B(n29574), .C(n27835), .D(n27994), 
         .Z(n28230)) /* synthesis lut_function=(!(A (B+!(C+(D))))) */ ;
    defparam i22164_4_lut.init = 16'h7775;
    LUT4 i14784_3_lut (.A(n15_adj_1678), .B(n29567), .C(cnt_main[4]), 
         .Z(n4519[1])) /* synthesis lut_function=(A (B)+!A (B (C))) */ ;
    defparam i14784_3_lut.init = 16'hc8c8;
    LUT4 i1_3_lut_adj_63 (.A(sys_clk_c_enable_136), .B(n29567), .C(n12_adj_1679), 
         .Z(sys_clk_c_enable_125)) /* synthesis lut_function=(!((B (C))+!A)) */ ;
    defparam i1_3_lut_adj_63.init = 16'h2a2a;
    LUT4 i2_3_lut_4_lut_4_lut_adj_64 (.A(state[4]), .B(state_back[5]), .C(state[2]), 
         .D(state[1]), .Z(n14)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;
    defparam i2_3_lut_4_lut_4_lut_adj_64.init = 16'h0004;
    LUT4 i25_4_lut (.A(n29703), .B(n29590), .C(cnt_main[4]), .D(n27909), 
         .Z(n12_adj_1679)) /* synthesis lut_function=(A (B (C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;
    defparam i25_4_lut.init = 16'hc0c5;
    LUT4 i1_2_lut_2_lut (.A(state[4]), .B(state_back[1]), .Z(n36)) /* synthesis lut_function=(!(A+!(B))) */ ;
    defparam i1_2_lut_2_lut.init = 16'h4444;
    LUT4 i2_3_lut_4_lut_4_lut_adj_65 (.A(state[4]), .B(state[5]), .C(n29621), 
         .D(state[3]), .Z(n11_adj_1680)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ;
    defparam i2_3_lut_4_lut_4_lut_adj_65.init = 16'hfffd;
    LUT4 i3_4_lut (.A(state[1]), .B(oled_csn_N_1597), .C(n29626), .D(n29674), 
         .Z(n27623)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i3_4_lut.init = 16'h0400;
    LUT4 i1_2_lut_3_lut_adj_66 (.A(n29567), .B(cnt_main[4]), .C(sys_clk_c_enable_136), 
         .Z(n22754)) /* synthesis lut_function=(A (B (C))+!A (C)) */ ;
    defparam i1_2_lut_3_lut_adj_66.init = 16'hd0d0;
    PFUMX i22704 (.BLUT(n29384), .ALUT(n29383), .C0(cnt_scan[3]), .Z(n29385));
    FD1P3IX num_2277__i3 (.D(n37[3]), .SP(sys_clk_c_enable_108), .CD(n16671), 
            .CK(sys_clk_c), .Q(num[3])) /* synthesis syn_use_carry_chain=1 */ ;
    defparam num_2277__i3.GSR = "ENABLED";
    LUT4 i2_3_lut_rep_271_3_lut (.A(n29567), .B(n23), .C(sys_clk_c_enable_136), 
         .Z(n29547)) /* synthesis lut_function=(A (B (C))+!A (C)) */ ;
    defparam i2_3_lut_rep_271_3_lut.init = 16'hd0d0;
    FD1P3IX cnt_i0_i15 (.D(n505[15]), .SP(sys_clk_c_enable_122), .CD(n16615), 
            .CK(sys_clk_c), .Q(cnt_c[15])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_i0_i15.GSR = "ENABLED";
    LUT4 i1_4_lut_adj_67 (.A(state[1]), .B(n10), .C(n29590), .D(cnt_main[4]), 
         .Z(n27520)) /* synthesis lut_function=(A (B+(C (D)+!C !(D)))) */ ;
    defparam i1_4_lut_adj_67.init = 16'ha88a;
    LUT4 i1_2_lut_rep_397 (.A(cnt_write[3]), .B(cnt_write[2]), .Z(n29673)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(153[7] 173[14])
    defparam i1_2_lut_rep_397.init = 16'heeee;
    PFUMX i22702 (.BLUT(n29381), .ALUT(n29284), .C0(cnt_scan[1]), .Z(n29382));
    LUT4 i1_2_lut_rep_350_3_lut (.A(cnt_write[3]), .B(cnt_write[2]), .C(cnt_write[1]), 
         .Z(n29626)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(153[7] 173[14])
    defparam i1_2_lut_rep_350_3_lut.init = 16'hfefe;
    LUT4 i21742_2_lut_rep_316_3_lut_4_lut (.A(cnt_write[3]), .B(cnt_write[2]), 
         .C(cnt_write[0]), .D(cnt_write[1]), .Z(n29592)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(153[7] 173[14])
    defparam i21742_2_lut_rep_316_3_lut_4_lut.init = 16'hfffe;
    LUT4 i1_4_lut_adj_68 (.A(cnt_init[0]), .B(num_delay[12]), .C(n29580), 
         .D(n29647), .Z(num_delay_15__N_1505[12])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D)))) */ ;
    defparam i1_4_lut_adj_68.init = 16'hcc40;
    LUT4 i1_4_lut_adj_69 (.A(state[2]), .B(n29591), .C(n19_adj_1681), 
         .D(n16_adj_1670), .Z(n6_adj_1682)) /* synthesis lut_function=(A (B+(C+(D)))) */ ;
    defparam i1_4_lut_adj_69.init = 16'haaa8;
    FD1P3AY state_i0_i0 (.D(n42_adj_1683), .SP(sys_clk_c_enable_83), .CK(sys_clk_c), 
            .Q(state[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam state_i0_i0.GSR = "ENABLED";
    LUT4 i1_2_lut_rep_398 (.A(state[4]), .B(cnt_write[0]), .Z(n29674)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i1_2_lut_rep_398.init = 16'h8888;
    LUT4 i2_4_lut_adj_70 (.A(sys_clk_c_enable_136), .B(n21361), .C(n29590), 
         .D(n4_adj_1684), .Z(sys_clk_c_enable_137)) /* synthesis lut_function=(A (B ((D)+!C))) */ ;
    defparam i2_4_lut_adj_70.init = 16'h8808;
    LUT4 i14797_3_lut (.A(n15_adj_1685), .B(n29567), .C(cnt_main[4]), 
         .Z(n6420[5])) /* synthesis lut_function=(A (B)+!A (B (C))) */ ;
    defparam i14797_3_lut.init = 16'hc8c8;
    LUT4 i15333_2_lut_rep_267_4_lut_4_lut (.A(n29567), .B(n21361), .C(n23), 
         .D(sys_clk_c_enable_136), .Z(sys_clk_c_enable_95)) /* synthesis lut_function=(A (B (C (D)))+!A (B (D))) */ ;
    defparam i15333_2_lut_rep_267_4_lut_4_lut.init = 16'hc400;
    PFUMX i68 (.BLUT(n25086), .ALUT(n36), .C0(state[5]), .Z(n44_adj_1686));
    LUT4 i1_2_lut_3_lut_adj_71 (.A(state[4]), .B(cnt_write[0]), .C(oled_csn_N_1597), 
         .Z(n27624)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i1_2_lut_3_lut_adj_71.init = 16'h0808;
    LUT4 i1_4_lut_adj_72 (.A(state[2]), .B(n29418), .C(char_reg_c[4]), 
         .D(n29576), .Z(n6_adj_1687)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))) */ ;
    defparam i1_4_lut_adj_72.init = 16'ha088;
    LUT4 i92_4_lut (.A(n25083), .B(n27805), .C(cnt_scan[1]), .D(n6_adj_1688), 
         .Z(n57)) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ;
    defparam i92_4_lut.init = 16'h3a0a;
    LUT4 i1_2_lut_rep_288 (.A(n2130), .B(num[4]), .Z(n29564)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[51:79])
    defparam i1_2_lut_rep_288.init = 16'h2222;
    LUT4 i14891_2_lut_rep_349_3_lut_4_lut (.A(state[4]), .B(state[5]), .C(state[0]), 
         .D(state[1]), .Z(n29625)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(67[5:9])
    defparam i14891_2_lut_rep_349_3_lut_4_lut.init = 16'hfffe;
    FD1P3IX cnt_i0_i14 (.D(n505[14]), .SP(sys_clk_c_enable_122), .CD(n16615), 
            .CK(sys_clk_c), .Q(cnt_c[14])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_i0_i14.GSR = "ENABLED";
    FD1P3IX cnt_i0_i13 (.D(n505[13]), .SP(sys_clk_c_enable_122), .CD(n16615), 
            .CK(sys_clk_c), .Q(cnt_c[13])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_i0_i13.GSR = "ENABLED";
    L6MUX21 i21961 (.D0(n28110), .D1(n28111), .SD(cnt_main[2]), .Z(n28112));
    LUT4 sign_bdd_4_lut (.A(sign), .B(cnt_main[2]), .C(cnt_main[1]), .D(\cnt_main[0] ), 
         .Z(n28973)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C+!(D)))+!A (B (C (D)+!C !(D))+!B !(C)))) */ ;
    defparam sign_bdd_4_lut.init = 16'h3cf2;
    FD1P3IX cnt_i0_i12 (.D(n505[12]), .SP(sys_clk_c_enable_122), .CD(n16615), 
            .CK(sys_clk_c), .Q(cnt_c[12])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_i0_i12.GSR = "ENABLED";
    FD1P3IX cnt_i0_i11 (.D(n505[11]), .SP(sys_clk_c_enable_122), .CD(n16615), 
            .CK(sys_clk_c), .Q(cnt_c[11])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_i0_i11.GSR = "ENABLED";
    LUT4 i2903_2_lut_3_lut_4_lut (.A(cnt_scan[1]), .B(cnt_scan[0]), .C(cnt_scan[3]), 
         .D(cnt_scan[2]), .Z(n653[3])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[24:39])
    defparam i2903_2_lut_3_lut_4_lut.init = 16'h78f0;
    LUT4 i2905_2_lut_3_lut_4_lut (.A(cnt_scan[1]), .B(cnt_scan[0]), .C(cnt_scan[3]), 
         .D(cnt_scan[2]), .Z(n8384)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[24:39])
    defparam i2905_2_lut_3_lut_4_lut.init = 16'h8000;
    L6MUX21 i21968 (.D0(n28117), .D1(n28118), .SD(cnt_main[2]), .Z(n28119));
    FD1P3IX cnt_i0_i10 (.D(n505[10]), .SP(sys_clk_c_enable_122), .CD(n16615), 
            .CK(sys_clk_c), .Q(cnt_c[10])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_i0_i10.GSR = "ENABLED";
    LUT4 i25_3_lut_4_lut (.A(cnt_scan[1]), .B(cnt_scan[0]), .C(cnt_scan[3]), 
         .D(cnt_scan[2]), .Z(n18_adj_1689)) /* synthesis lut_function=(A (B (C (D)+!C !(D))+!B (C (D)))+!A (C (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[24:39])
    defparam i25_3_lut_4_lut.init = 16'hf008;
    LUT4 i2896_2_lut_3_lut (.A(cnt_scan[1]), .B(cnt_scan[0]), .C(cnt_scan[2]), 
         .Z(n653[2])) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[24:39])
    defparam i2896_2_lut_3_lut.init = 16'h7878;
    LUT4 i1_2_lut_rep_403 (.A(cnt_scan[1]), .B(cnt_scan[0]), .Z(n29679)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(146[8:13])
    defparam i1_2_lut_rep_403.init = 16'heeee;
    LUT4 i1_3_lut_rep_374_4_lut (.A(cnt_scan[1]), .B(cnt_scan[0]), .C(cnt_scan[3]), 
         .D(cnt_scan[2]), .Z(n29650)) /* synthesis lut_function=(A+(B+!(C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(146[8:13])
    defparam i1_3_lut_rep_374_4_lut.init = 16'hefff;
    LUT4 i2_3_lut_4_lut_adj_73 (.A(cnt_scan[1]), .B(cnt_scan[0]), .C(cnt_scan[3]), 
         .D(cnt_scan[2]), .Z(n25417)) /* synthesis lut_function=(A (C (D))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(146[8:13])
    defparam i2_3_lut_4_lut_adj_73.init = 16'he000;
    LUT4 i72_2_lut_rep_405 (.A(state[0]), .B(state[4]), .Z(n29681)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i72_2_lut_rep_405.init = 16'h6666;
    LUT4 i14431_2_lut_rep_406 (.A(state[3]), .B(state[2]), .Z(n29682)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i14431_2_lut_rep_406.init = 16'heeee;
    LUT4 i14910_2_lut_3_lut_4_lut (.A(state[3]), .B(state[2]), .C(state[0]), 
         .D(state[1]), .Z(n20949)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i14910_2_lut_3_lut_4_lut.init = 16'hfffe;
    L6MUX21 i21971 (.D0(n28120), .D1(n28121), .SD(cnt_main[2]), .Z(n28122));
    LUT4 mux_19_Mux_1_i9_3_lut (.A(temp_l[1]), .B(temp_p[1]), .C(\cnt_main[0] ), 
         .Z(n9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam mux_19_Mux_1_i9_3_lut.init = 16'hcaca;
    LUT4 i21665_2_lut_3_lut_4_lut (.A(state[3]), .B(state[2]), .C(state[4]), 
         .D(state[0]), .Z(n27797)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i21665_2_lut_3_lut_4_lut.init = 16'hfffe;
    LUT4 i22232_2_lut_rep_407 (.A(cnt_main[4]), .B(cnt_main[3]), .Z(n29683)) /* synthesis lut_function=(!(A+(B))) */ ;
    defparam i22232_2_lut_rep_407.init = 16'h1111;
    LUT4 i2_3_lut_4_lut_adj_74 (.A(cnt_main[4]), .B(cnt_main[3]), .C(n29630), 
         .D(n29567), .Z(n6420[53])) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;
    defparam i2_3_lut_4_lut_adj_74.init = 16'h1000;
    L6MUX21 i22014 (.D0(n28163), .D1(n28164), .SD(cnt_write[3]), .Z(oled_dat_N_1635));
    L6MUX21 i22021 (.D0(n28170), .D1(n28171), .SD(cnt_main[2]), .Z(n28172));
    PFUMX i74 (.BLUT(n34), .ALUT(n41), .C0(state[5]), .Z(n50));
    PFUMX i38 (.BLUT(n13), .ALUT(n27602), .C0(state[4]), .Z(n23_adj_1690));
    FD1P3IX cnt_i0_i9 (.D(n505[9]), .SP(sys_clk_c_enable_122), .CD(n16615), 
            .CK(sys_clk_c), .Q(cnt_c[9])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_i0_i9.GSR = "ENABLED";
    LUT4 i14973_2_lut (.A(temp_h[1]), .B(\cnt_main[0] ), .Z(n8)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam i14973_2_lut.init = 16'h8888;
    LUT4 i3218_2_lut_rep_409 (.A(\cnt_main[0] ), .B(cnt_main[1]), .Z(n29685)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam i3218_2_lut_rep_409.init = 16'h6666;
    LUT4 i1_3_lut_4_lut (.A(sign), .B(n29623), .C(n29567), .D(cnt_main[4]), 
         .Z(n4_adj_1684)) /* synthesis lut_function=(!(A (C (D))+!A (B (C)+!B (C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam i1_3_lut_4_lut.init = 16'h0fbf;
    LUT4 i37_3_lut_4_lut (.A(sign), .B(n29623), .C(cnt_main[3]), .D(n27909), 
         .Z(n27911)) /* synthesis lut_function=(A (C+(D))+!A !(B (C+!(D))+!B !(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam i37_3_lut_4_lut.init = 16'hbfb0;
    FD1P3AY oled_clk_305 (.D(n27067), .SP(sys_clk_c_enable_29), .CK(sys_clk_c), 
            .Q(OLED_bus_c_0)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam oled_clk_305.GSR = "ENABLED";
    FD1P3AY oled_rst_303 (.D(n5492[0]), .SP(sys_clk_c_enable_30), .CK(sys_clk_c), 
            .Q(OLED_bus_c_2)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam oled_rst_303.GSR = "ENABLED";
    LUT4 mux_14_Mux_3_i15_4_lut_4_lut (.A(sign), .B(n29623), .C(cnt_main[3]), 
         .D(state[3]), .Z(n15)) /* synthesis lut_function=(A ((C)+!B)+!A ((C (D))+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam mux_14_Mux_3_i15_4_lut_4_lut.init = 16'hf3b3;
    LUT4 i2855_2_lut_rep_415 (.A(cnt_init[1]), .B(cnt_init[0]), .Z(n29691)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(109[49:64])
    defparam i2855_2_lut_rep_415.init = 16'h8888;
    LUT4 i2867_2_lut_3_lut_4_lut (.A(cnt_init[1]), .B(cnt_init[0]), .C(cnt_init[3]), 
         .D(cnt_init[2]), .Z(n443[3])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(109[49:64])
    defparam i2867_2_lut_3_lut_4_lut.init = 16'h78f0;
    LUT4 i2860_2_lut_3_lut (.A(cnt_init[1]), .B(cnt_init[0]), .C(cnt_init[2]), 
         .Z(n443[2])) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(109[49:64])
    defparam i2860_2_lut_3_lut.init = 16'h7878;
    LUT4 n1011_bdd_4_lut (.A(n1767), .B(n2523), .C(cnt_scan[3]), .D(cnt_scan[1]), 
         .Z(n30751)) /* synthesis lut_function=(A (B (C)+!B !((D)+!C))+!A (B (C (D)))) */ ;
    defparam n1011_bdd_4_lut.init = 16'hc0a0;
    LUT4 i2_3_lut_rep_290_4_lut (.A(state[2]), .B(n29622), .C(n29666), 
         .D(n29621), .Z(sys_clk_c_enable_136)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;
    defparam i2_3_lut_rep_290_4_lut.init = 16'h0100;
    LUT4 i1_4_lut_adj_75 (.A(state[0]), .B(num_delay[15]), .C(n16_adj_1691), 
         .D(n19), .Z(num_delay_15__N_1194[15])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_75.init = 16'hdc50;
    LUT4 i2_3_lut_4_lut_adj_76 (.A(cnt_init[0]), .B(state[2]), .C(cnt_init[2]), 
         .D(n29699), .Z(n27642)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;
    defparam i2_3_lut_4_lut_adj_76.init = 16'h0004;
    FD1P3AX cnt_main_i0_i0 (.D(n75), .SP(sys_clk_c_enable_136), .CK(sys_clk_c), 
            .Q(\cnt_main[0] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_main_i0_i0.GSR = "ENABLED";
    LUT4 n1389_bdd_4_lut_23363 (.A(n1389), .B(n2145), .C(cnt_scan[3]), 
         .D(cnt_scan[1]), .Z(n30753)) /* synthesis lut_function=(A (B (C)+!B !((D)+!C))+!A (B (C (D)))) */ ;
    defparam n1389_bdd_4_lut_23363.init = 16'hc0a0;
    LUT4 i21965_3_lut (.A(min_h[2]), .B(min_l[2]), .C(\cnt_main[0] ), 
         .Z(n28116)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i21965_3_lut.init = 16'hcaca;
    LUT4 i21964_3_lut (.A(\hour_h[2] ), .B(\hour_l[2] ), .C(\cnt_main[0] ), 
         .Z(n28115)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i21964_3_lut.init = 16'hcaca;
    LUT4 n1011_bdd_3_lut (.A(n1011), .B(cnt_scan[3]), .C(cnt_scan[1]), 
         .Z(n30750)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;
    defparam n1011_bdd_3_lut.init = 16'h2020;
    LUT4 i1_4_lut_adj_77 (.A(n19_adj_1692), .B(cnt[4]), .C(n20), .D(n4), 
         .Z(oled_dcn_N_1613)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_77.init = 16'hfefa;
    LUT4 i22221_3_lut_rep_291_4_lut (.A(state[2]), .B(n29622), .C(state[1]), 
         .D(state[0]), .Z(n29567)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;
    defparam i22221_3_lut_rep_291_4_lut.init = 16'h0010;
    LUT4 i8_4_lut (.A(cnt_c[5]), .B(cnt_c[11]), .C(cnt_c[10]), .D(cnt_c[13]), 
         .Z(n19_adj_1692)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i8_4_lut.init = 16'hfffe;
    LUT4 cnt_main_0__bdd_4_lut (.A(cnt_main[3]), .B(cnt_main[2]), .C(cnt_main[1]), 
         .D(sign), .Z(n29008)) /* synthesis lut_function=(A (B (C)+!B !(C+!(D)))+!A (B (C))) */ ;
    defparam cnt_main_0__bdd_4_lut.init = 16'hc2c0;
    CCU2D add_26_7 (.A0(cnt_c[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_c[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n24946), 
          .COUT(n24947), .S0(n479[5]), .S1(n479[6]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam add_26_7.INIT0 = 16'h5aaa;
    defparam add_26_7.INIT1 = 16'h5aaa;
    defparam add_26_7.INJECT1_0 = "NO";
    defparam add_26_7.INJECT1_1 = "NO";
    LUT4 n30755_bdd_2_lut (.A(n30755), .B(cnt_scan[4]), .Z(n30756)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam n30755_bdd_2_lut.init = 16'h2222;
    CCU2D add_26_5 (.A0(cnt[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n24945), 
          .COUT(n24946), .S0(n479[3]), .S1(n479[4]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam add_26_5.INIT0 = 16'h5aaa;
    defparam add_26_5.INIT1 = 16'h5aaa;
    defparam add_26_5.INJECT1_0 = "NO";
    defparam add_26_5.INJECT1_1 = "NO";
    CCU2D add_26_3 (.A0(\cnt[1] ), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(\cnt[2] ), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n24944), 
          .COUT(n24945), .S0(n479[1]), .S1(n479[2]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam add_26_3.INIT0 = 16'h5aaa;
    defparam add_26_3.INIT1 = 16'h5aaa;
    defparam add_26_3.INJECT1_0 = "NO";
    defparam add_26_3.INJECT1_1 = "NO";
    LUT4 i9_4_lut (.A(cnt_c[9]), .B(n18_adj_1694), .C(cnt_c[8]), .D(cnt_c[6]), 
         .Z(n20)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i9_4_lut.init = 16'hfffe;
    LUT4 i7_4_lut (.A(cnt_c[7]), .B(cnt_c[14]), .C(cnt_c[12]), .D(cnt_c[15]), 
         .Z(n18_adj_1694)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i7_4_lut.init = 16'hfffe;
    LUT4 i33_4_lut_adj_78 (.A(num_delay[15]), .B(num_delay_15__N_1505[15]), 
         .C(state[2]), .D(n20968), .Z(n16_adj_1691)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_78.init = 16'h0aca;
    CCU2D add_26_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(\cnt[0] ), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n24944), 
          .S1(n479[0]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam add_26_1.INIT0 = 16'hF000;
    defparam add_26_1.INIT1 = 16'h5555;
    defparam add_26_1.INJECT1_0 = "NO";
    defparam add_26_1.INJECT1_1 = "NO";
    FD1P3IX cnt_i0_i8 (.D(n505[8]), .SP(sys_clk_c_enable_122), .CD(n16615), 
            .CK(sys_clk_c), .Q(cnt_c[8])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_i0_i8.GSR = "ENABLED";
    LUT4 char_5__bdd_3_lut (.A(num[1]), .B(char[13]), .C(char[53]), .Z(n29465)) /* synthesis lut_function=(A (C)+!A (B)) */ ;
    defparam char_5__bdd_3_lut.init = 16'he4e4;
    LUT4 cnt_2__bdd_4_lut (.A(\cnt[2] ), .B(\cnt[0] ), .C(cnt[4]), .D(cnt[3]), 
         .Z(n30782)) /* synthesis lut_function=(!(A (B+(C+(D)))+!A (B (C+!(D))+!B !((D)+!C)))) */ ;
    defparam cnt_2__bdd_4_lut.init = 16'h1503;
    LUT4 cnt_main_0__bdd_3_lut_22736 (.A(cnt_main[3]), .B(cnt_main[2]), 
         .C(cnt_main[1]), .Z(n29007)) /* synthesis lut_function=(!(A (B+!(C))+!A ((C)+!B))) */ ;
    defparam cnt_main_0__bdd_3_lut_22736.init = 16'h2424;
    LUT4 cnt_2__bdd_3_lut (.A(\cnt[2] ), .B(cnt[4]), .C(cnt[3]), .Z(n30781)) /* synthesis lut_function=(!((B+(C))+!A)) */ ;
    defparam cnt_2__bdd_3_lut.init = 16'h0202;
    FD1P3IX cnt_i0_i7 (.D(n505[7]), .SP(sys_clk_c_enable_122), .CD(n16615), 
            .CK(sys_clk_c), .Q(cnt_c[7])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_i0_i7.GSR = "ENABLED";
    LUT4 cnt_init_2__bdd_4_lut_22657 (.A(cnt_init[2]), .B(cnt_init[1]), 
         .C(cnt_init[0]), .D(n29702), .Z(n29037)) /* synthesis lut_function=(A (B+((D)+!C))+!A (B ((D)+!C)+!B (C+(D)))) */ ;
    defparam cnt_init_2__bdd_4_lut_22657.init = 16'hff9e;
    LUT4 i1_4_lut_adj_79 (.A(cnt_init[0]), .B(num_delay[15]), .C(n29580), 
         .D(n29647), .Z(num_delay_15__N_1505[15])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D)))) */ ;
    defparam i1_4_lut_adj_79.init = 16'hcc40;
    LUT4 n30818_bdd_2_lut (.A(n30818), .B(cnt_scan[2]), .Z(n30819)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam n30818_bdd_2_lut.init = 16'h2222;
    FD1P3IX cnt_i0_i6 (.D(n505[6]), .SP(sys_clk_c_enable_122), .CD(n16615), 
            .CK(sys_clk_c), .Q(cnt_c[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_i0_i6.GSR = "ENABLED";
    LUT4 i1_4_lut_adj_80 (.A(n38_adj_1695), .B(n41_adj_1696), .C(n29682), 
         .D(n29671), .Z(n47)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A ((D)+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i1_4_lut_adj_80.init = 16'h0ace;
    LUT4 i2_3_lut_3_lut_4_lut (.A(n2132), .B(num[4]), .C(n2130), .D(n2131), 
         .Z(n11124)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[59:71])
    defparam i2_3_lut_3_lut_4_lut.init = 16'hfffd;
    LUT4 i1_2_lut_4_lut_4_lut (.A(\cnt_main[0] ), .B(cnt_main[1]), .C(cnt_main[2]), 
         .D(state[0]), .Z(n4_adj_1697)) /* synthesis lut_function=(!(A (B (C+(D))+!B (D))+!A (B (D)+!B ((D)+!C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam i1_2_lut_4_lut_4_lut.init = 16'h007e;
    LUT4 n847_bdd_4_lut_22723_4_lut (.A(n2132), .B(num[4]), .C(n2131), 
         .D(n29584), .Z(n28763)) /* synthesis lut_function=(A (B (C (D))+!B !(C+(D)))+!A (C (D))) */ ;
    defparam n847_bdd_4_lut_22723_4_lut.init = 16'hd002;
    LUT4 n1676_bdd_2_lut_22735_2_lut_4_lut (.A(cnt_scan[2]), .B(n29421), 
         .C(n27632), .D(cnt_scan[1]), .Z(n29423)) /* synthesis lut_function=(!(A+!(B (C+!(D))+!B (C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(146[8:13])
    defparam n1676_bdd_2_lut_22735_2_lut_4_lut.init = 16'h5044;
    LUT4 i66_4_lut (.A(state[0]), .B(cnt_main[4]), .C(state[1]), .D(n29568), 
         .Z(n38_adj_1695)) /* synthesis lut_function=(!(A (C)+!A (B+((D)+!C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i66_4_lut.init = 16'h0a1a;
    LUT4 i97_4_lut_4_lut_4_lut (.A(cnt_scan[0]), .B(y_p[4]), .C(cnt_scan[2]), 
         .D(n1013), .Z(n45_adj_1698)) /* synthesis lut_function=(A (C (D))+!A !((C)+!B)) */ ;
    defparam i97_4_lut_4_lut_4_lut.init = 16'ha404;
    LUT4 n1014_bdd_4_lut (.A(n1014), .B(cnt_scan[2]), .C(x_pl[3]), .D(cnt_scan[1]), 
         .Z(n30820)) /* synthesis lut_function=(A (B (D)+!B !((D)+!C))+!A !(B+((D)+!C))) */ ;
    defparam n1014_bdd_4_lut.init = 16'h8830;
    PFUMX i21959 (.BLUT(n28106), .ALUT(n28107), .C0(cnt_main[1]), .Z(n28110));
    LUT4 n1392_bdd_3_lut (.A(n1392), .B(n2148), .C(cnt_scan[1]), .Z(n30817)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n1392_bdd_3_lut.init = 16'hcaca;
    PFUMX i22628 (.BLUT(n29277), .ALUT(n29276), .C0(cnt_scan[1]), .Z(n29278));
    LUT4 i14749_2_lut (.A(n479[1]), .B(oled_dcn_N_1613), .Z(n505[1])) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam i14749_2_lut.init = 16'h2222;
    LUT4 i22165_2_lut_4_lut (.A(n29621), .B(n29589), .C(n29666), .D(n28230), 
         .Z(sys_clk_c_enable_123)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;
    defparam i22165_2_lut_4_lut.init = 16'h0200;
    LUT4 i10578_2_lut (.A(sys_clk_c_enable_83), .B(state[0]), .Z(n16652)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam i10578_2_lut.init = 16'h8888;
    LUT4 i22097_1_lut_4_lut_4_lut_4_lut (.A(num[4]), .B(n27885), .C(n2131), 
         .D(n2130), .Z(n28193)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;
    defparam i22097_1_lut_4_lut_4_lut_4_lut.init = 16'h0100;
    LUT4 i22179_2_lut_4_lut (.A(n29621), .B(n29589), .C(n29666), .D(n28244), 
         .Z(sys_clk_c_enable_116)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;
    defparam i22179_2_lut_4_lut.init = 16'h0200;
    LUT4 i22161_2_lut_4_lut (.A(n29621), .B(n29589), .C(n29666), .D(n28226), 
         .Z(sys_clk_c_enable_14)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;
    defparam i22161_2_lut_4_lut.init = 16'h0200;
    LUT4 i1_4_lut_then_4_lut (.A(n27907), .B(state[2]), .C(state[3]), 
         .D(state[0]), .Z(n29725)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;
    defparam i1_4_lut_then_4_lut.init = 16'h0001;
    LUT4 i1_2_lut_rep_279_4_lut (.A(n29589), .B(state[0]), .C(state[1]), 
         .D(cnt_main[4]), .Z(n29555)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ;
    defparam i1_2_lut_rep_279_4_lut.init = 16'hffef;
    LUT4 i1_4_lut_else_4_lut (.A(n27907), .B(state[2]), .C(state[3]), 
         .D(state[0]), .Z(n29724)) /* synthesis lut_function=(!(A+(B (C+(D))+!B (C (D)+!C !(D))))) */ ;
    defparam i1_4_lut_else_4_lut.init = 16'h0114;
    FD1P3IX cnt_delay_i0_i0 (.D(n2606[0]), .SP(sys_clk_c_enable_131), .CD(n16582), 
            .CK(sys_clk_c), .Q(cnt_delay[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_delay_i0_i0.GSR = "ENABLED";
    LUT4 i1_2_lut_rep_278_4_lut (.A(n29589), .B(state[0]), .C(state[1]), 
         .D(cnt_main[2]), .Z(n29554)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;
    defparam i1_2_lut_rep_278_4_lut.init = 16'h1000;
    LUT4 i1_4_lut_adj_81 (.A(n20_adj_1699), .B(state[3]), .C(n29712), 
         .D(n23_adj_1690), .Z(n25871)) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i1_4_lut_adj_81.init = 16'h3b0a;
    LUT4 i2_4_lut_adj_82 (.A(n32), .B(n20600), .C(n30), .D(state[5]), 
         .Z(n39)) /* synthesis lut_function=(!(A (B+!(C+!(D)))+!A (B+!(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i2_4_lut_adj_82.init = 16'h3022;
    LUT4 n29638_bdd_4_lut (.A(n29638), .B(state[2]), .C(cnt_init[0]), 
         .D(n29624), .Z(n29728)) /* synthesis lut_function=(!(A ((C+(D))+!B)+!A ((C)+!B))) */ ;
    defparam n29638_bdd_4_lut.init = 16'h040c;
    LUT4 i14561_2_lut (.A(state[4]), .B(state[3]), .Z(n20600)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i14561_2_lut.init = 16'heeee;
    LUT4 i2_4_lut_adj_83 (.A(n13_adj_1700), .B(n20600), .C(n11_c), .D(state[5]), 
         .Z(n39_adj_1701)) /* synthesis lut_function=(!(A (B+!(C+!(D)))+!A (B+!(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i2_4_lut_adj_83.init = 16'h3022;
    LUT4 i7419_4_lut_then_4_lut (.A(n2131), .B(num[4]), .C(n2130), .D(n2132), 
         .Z(n29733)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[51:79])
    defparam i7419_4_lut_then_4_lut.init = 16'h0100;
    LUT4 i7419_4_lut_else_4_lut (.A(n2131), .B(num[4]), .C(n2130), .D(n2132), 
         .Z(n29732)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[51:79])
    defparam i7419_4_lut_else_4_lut.init = 16'h0020;
    LUT4 i21821_3_lut_3_lut_4_lut (.A(n29623), .B(cnt_main[3]), .C(n27911), 
         .D(cnt_main[4]), .Z(n27969)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C+(D)))+!A ((D)+!C))) */ ;
    defparam i21821_3_lut_3_lut_4_lut.init = 16'h22f0;
    LUT4 n27745_bdd_4_lut_then_3_lut (.A(cnt_main[2]), .B(cnt_main[3]), 
         .C(cnt_main[1]), .Z(n29736)) /* synthesis lut_function=(!(A (B+!(C))+!A !(B+(C)))) */ ;
    defparam n27745_bdd_4_lut_then_3_lut.init = 16'h7474;
    FD1P3IX cnt_i0_i5 (.D(n505[5]), .SP(sys_clk_c_enable_122), .CD(n16615), 
            .CK(sys_clk_c), .Q(cnt_c[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_i0_i5.GSR = "ENABLED";
    LUT4 n27745_bdd_4_lut_else_3_lut (.A(cnt_main[2]), .B(cnt_main[3]), 
         .C(cnt_main[1]), .D(sign), .Z(n29735)) /* synthesis lut_function=(!(A (B)+!A !(B (C+(D))))) */ ;
    defparam n27745_bdd_4_lut_else_3_lut.init = 16'h6662;
    LUT4 n1392_bdd_3_lut_23366 (.A(n1770), .B(n2526), .C(cnt_scan[1]), 
         .Z(n30816)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n1392_bdd_3_lut_23366.init = 16'hcaca;
    LUT4 n1676_bdd_2_lut_23377 (.A(n30820), .B(cnt_scan[0]), .Z(n30821)) /* synthesis lut_function=(A (B)) */ ;
    defparam n1676_bdd_2_lut_23377.init = 16'h8888;
    LUT4 i22250_4_lut_then_3_lut (.A(n29590), .B(state[3]), .C(state[0]), 
         .Z(n29739)) /* synthesis lut_function=((B+(C))+!A) */ ;
    defparam i22250_4_lut_then_3_lut.init = 16'hfdfd;
    LUT4 i22250_4_lut_else_3_lut (.A(n29623), .B(state[3]), .C(n29703), 
         .D(state[0]), .Z(n29738)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ;
    defparam i22250_4_lut_else_3_lut.init = 16'hfffd;
    LUT4 i1_2_lut_4_lut_adj_84 (.A(state[2]), .B(n30783), .C(char_reg_c[5]), 
         .D(n29576), .Z(n6_adj_1702)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))) */ ;
    defparam i1_2_lut_4_lut_adj_84.init = 16'ha088;
    LUT4 i1_2_lut_4_lut_adj_85 (.A(n22), .B(n2054), .C(n28077), .D(state[2]), 
         .Z(n6_adj_1703)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A !((C+!(D))+!B)) */ ;
    defparam i1_2_lut_4_lut_adj_85.init = 16'hac00;
    FD1P3IX cnt_i0_i4 (.D(n505[4]), .SP(sys_clk_c_enable_122), .CD(n16615), 
            .CK(sys_clk_c), .Q(cnt[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_i0_i4.GSR = "ENABLED";
    LUT4 i22159_3_lut_4_lut (.A(n27642), .B(n5534), .C(n29596), .D(n7507), 
         .Z(sys_clk_c_enable_30)) /* synthesis lut_function=(A (B (C+(D)))+!A !((C+!(D))+!B)) */ ;
    defparam i22159_3_lut_4_lut.init = 16'h8c80;
    FD1P3AX y_p_i0_i0 (.D(n4593[0]), .SP(sys_clk_c_enable_38), .CK(sys_clk_c), 
            .Q(y_p[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam y_p_i0_i0.GSR = "ENABLED";
    FD1P3IX cnt_i0_i3 (.D(n505[3]), .SP(sys_clk_c_enable_122), .CD(n16615), 
            .CK(sys_clk_c), .Q(cnt[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_i0_i3.GSR = "ENABLED";
    LUT4 n29395_bdd_3_lut_then_4_lut (.A(cnt[3]), .B(\cnt[1] ), .C(\cnt[2] ), 
         .D(cnt[4]), .Z(n29718)) /* synthesis lut_function=(!(A+(B ((D)+!C)+!B (C (D)+!C !(D))))) */ ;
    defparam n29395_bdd_3_lut_then_4_lut.init = 16'h0150;
    LUT4 i2_2_lut_rep_317_4_lut (.A(n29699), .B(cnt_init[1]), .C(cnt_init[2]), 
         .D(cnt_init[0]), .Z(n29593)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;
    defparam i2_2_lut_rep_317_4_lut.init = 16'h0010;
    LUT4 i29_3_lut_4_lut_4_lut (.A(n29623), .B(cnt_main[3]), .C(cnt_main[4]), 
         .D(n29588), .Z(n23)) /* synthesis lut_function=(!(A (B (C+!(D)))+!A (B (C+!(D))+!B (C)))) */ ;
    defparam i29_3_lut_4_lut_4_lut.init = 16'h2f23;
    PFUMX i21960 (.BLUT(n28108), .ALUT(n28109), .C0(cnt_main[1]), .Z(n28111));
    LUT4 i1_2_lut_adj_86 (.A(state[0]), .B(cnt_main[4]), .Z(n27638)) /* synthesis lut_function=(!(A+!(B))) */ ;
    defparam i1_2_lut_adj_86.init = 16'h4444;
    LUT4 i1_2_lut_4_lut_adj_87 (.A(cnt_init[2]), .B(n29702), .C(cnt_init[0]), 
         .D(state_back[4]), .Z(n19_adj_1704)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (B (D))) */ ;
    defparam i1_2_lut_4_lut_adj_87.init = 16'hec00;
    LUT4 i1_2_lut_4_lut_adj_88 (.A(cnt_init[2]), .B(n29702), .C(cnt_init[0]), 
         .D(state_back[2]), .Z(n19_adj_1681)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (B (D))) */ ;
    defparam i1_2_lut_4_lut_adj_88.init = 16'hec00;
    LUT4 i36_3_lut_4_lut (.A(n29623), .B(cnt_main[3]), .C(cnt_main[4]), 
         .D(n27911), .Z(n21)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (C+!(D))) */ ;
    defparam i36_3_lut_4_lut.init = 16'hd0df;
    LUT4 i22018_3_lut (.A(min_h[0]), .B(min_l[0]), .C(\cnt_main[0] ), 
         .Z(n28169)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i22018_3_lut.init = 16'hcaca;
    LUT4 i22017_3_lut (.A(\hour_h[0] ), .B(\hour_l[0] ), .C(\cnt_main[0] ), 
         .Z(n28168)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i22017_3_lut.init = 16'hcaca;
    FD1P3IX cnt_i0_i2 (.D(n505[2]), .SP(sys_clk_c_enable_122), .CD(n16615), 
            .CK(sys_clk_c), .Q(\cnt[2] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_i0_i2.GSR = "ENABLED";
    LUT4 i1_2_lut_4_lut_adj_89 (.A(cnt_init[2]), .B(n29702), .C(cnt_init[0]), 
         .D(state_back[5]), .Z(n19_adj_1705)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (B (D))) */ ;
    defparam i1_2_lut_4_lut_adj_89.init = 16'hec00;
    LUT4 i1_2_lut_4_lut_adj_90 (.A(cnt_init[2]), .B(n29702), .C(cnt_init[0]), 
         .D(state_back[0]), .Z(n19_adj_1706)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (B (D))) */ ;
    defparam i1_2_lut_4_lut_adj_90.init = 16'hec00;
    CCU2D sub_1769_add_2_17 (.A0(cnt_delay[15]), .B0(num_delay[15]), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n24994), .S1(n2604));
    defparam sub_1769_add_2_17.INIT0 = 16'h5999;
    defparam sub_1769_add_2_17.INIT1 = 16'h0000;
    defparam sub_1769_add_2_17.INJECT1_0 = "NO";
    defparam sub_1769_add_2_17.INJECT1_1 = "NO";
    LUT4 i14421_2_lut_rep_423 (.A(cnt_init[4]), .B(cnt_init[3]), .Z(n29699)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i14421_2_lut_rep_423.init = 16'heeee;
    LUT4 i10545_3_lut_4_lut (.A(n29592), .B(oled_csn_N_1597), .C(n11_adj_1680), 
         .D(sys_clk_c_enable_121), .Z(n16617)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (C (D))) */ ;
    defparam i10545_3_lut_4_lut.init = 16'hf800;
    LUT4 i2_3_lut_4_lut_adj_91 (.A(state[3]), .B(n29621), .C(state[5]), 
         .D(state[4]), .Z(n11_adj_1707)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam i2_3_lut_4_lut_adj_91.init = 16'hffef;
    LUT4 i21809_3_lut_4_lut (.A(n29592), .B(oled_csn_N_1597), .C(state[2]), 
         .D(n27907), .Z(n27602)) /* synthesis lut_function=(!(A (B+(C+(D)))+!A (C+(D)))) */ ;
    defparam i21809_3_lut_4_lut.init = 16'h0007;
    LUT4 i1_2_lut_3_lut_adj_92 (.A(cnt_init[4]), .B(cnt_init[3]), .C(state[2]), 
         .Z(n4_adj_1674)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;
    defparam i1_2_lut_3_lut_adj_92.init = 16'h1010;
    LUT4 i2_3_lut_rep_370_4_lut (.A(cnt_init[4]), .B(cnt_init[3]), .C(cnt_init[2]), 
         .D(cnt_init[1]), .Z(n29646)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;
    defparam i2_3_lut_rep_370_4_lut.init = 16'h0010;
    LUT4 i2_3_lut_4_lut_adj_93 (.A(n29592), .B(oled_csn_N_1597), .C(state[1]), 
         .D(state[4]), .Z(n25086)) /* synthesis lut_function=(!(A (B+!(C (D)))+!A !(C (D)))) */ ;
    defparam i2_3_lut_4_lut_adj_93.init = 16'h7000;
    LUT4 i2946_3_lut_4_lut (.A(cnt_write[2]), .B(n29707), .C(cnt_write[3]), 
         .D(oled_csn_N_1597), .Z(n2582[4])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(152[25:41])
    defparam i2946_3_lut_4_lut.init = 16'h7f80;
    LUT4 i1_4_lut_adj_94 (.A(state[0]), .B(num_delay[13]), .C(n16_adj_1708), 
         .D(n19), .Z(num_delay_15__N_1194[13])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_94.init = 16'hdc50;
    LUT4 i33_4_lut_adj_95 (.A(num_delay[13]), .B(num_delay_15__N_1505[13]), 
         .C(state[2]), .D(n20968), .Z(n16_adj_1708)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_95.init = 16'h0aca;
    LUT4 mux_16_Mux_1_i15_3_lut_4_lut (.A(n29685), .B(cnt_main[2]), .C(cnt_main[3]), 
         .D(n29630), .Z(n15_adj_1678)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C (D)))+!A (C (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam mux_16_Mux_1_i15_3_lut_4_lut.init = 16'hf808;
    LUT4 i22229_4_lut_4_lut (.A(n29594), .B(n29704), .C(n21), .D(n29712), 
         .Z(sys_clk_c_enable_16)) /* synthesis lut_function=(!(A+(B (D)+!B (C+(D))))) */ ;
    defparam i22229_4_lut_4_lut.init = 16'h0045;
    LUT4 i1_3_lut_3_lut (.A(n29567), .B(sys_clk_c_enable_136), .C(n12995), 
         .Z(sys_clk_c_enable_15)) /* synthesis lut_function=(A (B (C))+!A (B)) */ ;
    defparam i1_3_lut_3_lut.init = 16'hc4c4;
    FD1P3AX state_i0_i1 (.D(n7769), .SP(sys_clk_c_enable_83), .CK(sys_clk_c), 
            .Q(state[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam state_i0_i1.GSR = "ENABLED";
    LUT4 n27623_bdd_3_lut_4_lut (.A(cnt_init[0]), .B(n29624), .C(state[1]), 
         .D(state[4]), .Z(n29520)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;
    defparam n27623_bdd_3_lut_4_lut.init = 16'h0002;
    LUT4 i2_4_lut_adj_96 (.A(cnt_init[0]), .B(n4_adj_1709), .C(num_delay[13]), 
         .D(n29580), .Z(num_delay_15__N_1505[13])) /* synthesis lut_function=(A (B)+!A (B+(C (D)))) */ ;
    defparam i2_4_lut_adj_96.init = 16'hdccc;
    LUT4 i1_2_lut_rep_425 (.A(cnt_init[2]), .B(cnt_init[1]), .Z(n29701)) /* synthesis lut_function=((B)+!A) */ ;
    defparam i1_2_lut_rep_425.init = 16'hdddd;
    FD1P3IX cnt_i0_i1 (.D(n505[1]), .SP(sys_clk_c_enable_122), .CD(n16615), 
            .CK(sys_clk_c), .Q(\cnt[1] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_i0_i1.GSR = "ENABLED";
    FD1P3IX state_i0_i5 (.D(n29523), .SP(sys_clk_c_enable_83), .CD(n16652), 
            .CK(sys_clk_c), .Q(state[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam state_i0_i5.GSR = "ENABLED";
    LUT4 i1_3_lut_rep_304_4_lut (.A(cnt_init[2]), .B(cnt_init[1]), .C(oled_dcn_N_1613), 
         .D(n29646), .Z(n29580)) /* synthesis lut_function=((B+(C (D)))+!A) */ ;
    defparam i1_3_lut_rep_304_4_lut.init = 16'hfddd;
    FD1P3IX state_i0_i4 (.D(n25871), .SP(sys_clk_c_enable_83), .CD(n16652), 
            .CK(sys_clk_c), .Q(state[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam state_i0_i4.GSR = "ENABLED";
    FD1P3IX state_i0_i3 (.D(n39), .SP(sys_clk_c_enable_83), .CD(n16652), 
            .CK(sys_clk_c), .Q(state[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam state_i0_i3.GSR = "ENABLED";
    FD1P3IX state_i0_i2 (.D(n39_adj_1701), .SP(sys_clk_c_enable_83), .CD(n16652), 
            .CK(sys_clk_c), .Q(state[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam state_i0_i2.GSR = "ENABLED";
    LUT4 i2874_3_lut_4_lut (.A(cnt_init[2]), .B(n29691), .C(cnt_init[3]), 
         .D(cnt_init[4]), .Z(n443[4])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(109[49:64])
    defparam i2874_3_lut_4_lut.init = 16'h7f80;
    LUT4 i2_2_lut_rep_335_4_lut (.A(cnt_scan[2]), .B(n29679), .C(cnt_scan[3]), 
         .D(cnt_scan[4]), .Z(n29611)) /* synthesis lut_function=((B+((D)+!C))+!A) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(145[8:13])
    defparam i2_2_lut_rep_335_4_lut.init = 16'hffdf;
    LUT4 i22016_3_lut (.A(temp_l[0]), .B(temp_p[0]), .C(\cnt_main[0] ), 
         .Z(n28167)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i22016_3_lut.init = 16'hcaca;
    LUT4 i1_2_lut_rep_375 (.A(cnt_scan[3]), .B(n15356), .Z(n29651)) /* synthesis lut_function=((B)+!A) */ ;
    defparam i1_2_lut_rep_375.init = 16'hdddd;
    LUT4 i1_2_lut_3_lut_4_lut (.A(cnt_scan[3]), .B(n15356), .C(n29650), 
         .D(cnt_scan[4]), .Z(n4_adj_1710)) /* synthesis lut_function=(A (B (C+(D)))+!A (C+(D))) */ ;
    defparam i1_2_lut_3_lut_4_lut.init = 16'hddd0;
    LUT4 i22015_3_lut (.A(sign), .B(temp_h[0]), .C(\cnt_main[0] ), .Z(n28166)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i22015_3_lut.init = 16'hcaca;
    LUT4 i1_3_lut_4_lut_adj_97 (.A(cnt_init[0]), .B(n29624), .C(n29647), 
         .D(num_delay[13]), .Z(n4_adj_1709)) /* synthesis lut_function=(A ((C (D))+!B)+!A (C (D))) */ ;
    defparam i1_3_lut_4_lut_adj_97.init = 16'hf222;
    LUT4 i1_2_lut_4_lut_adj_98 (.A(n28744), .B(n2048), .C(n28063), .D(state[2]), 
         .Z(n6_adj_1711)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A !((C+!(D))+!B)) */ ;
    defparam i1_2_lut_4_lut_adj_98.init = 16'hac00;
    FD1P3AX num_2277__i1 (.D(n1[1]), .SP(sys_clk_c_enable_92), .CK(sys_clk_c), 
            .Q(num[1])) /* synthesis syn_use_carry_chain=1 */ ;
    defparam num_2277__i1.GSR = "ENABLED";
    FD1P3AX num_2277__i2 (.D(n1[2]), .SP(sys_clk_c_enable_92), .CK(sys_clk_c), 
            .Q(num[2])) /* synthesis syn_use_carry_chain=1 */ ;
    defparam num_2277__i2.GSR = "ENABLED";
    LUT4 i1_2_lut_4_lut_adj_99 (.A(n29719), .B(char_reg_c[0]), .C(n29576), 
         .D(state[2]), .Z(n6_adj_1712)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ;
    defparam i1_2_lut_4_lut_adj_99.init = 16'hca00;
    LUT4 cnt_init_4__I_0_331_i7_2_lut_rep_426 (.A(cnt_init[3]), .B(cnt_init[4]), 
         .Z(n29702)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(109[8:12])
    defparam cnt_init_4__I_0_331_i7_2_lut_rep_426.init = 16'heeee;
    LUT4 i13_1_lut (.A(cnt_write[0]), .Z(n13_adj_1713)) /* synthesis lut_function=(!(A)) */ ;
    defparam i13_1_lut.init = 16'h5555;
    LUT4 i2_3_lut_rep_377 (.A(num[2]), .B(num[1]), .C(num[0]), .Z(n29653)) /* synthesis lut_function=(A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[59:71])
    defparam i2_3_lut_rep_377.init = 16'h8080;
    LUT4 i14590_2_lut_4_lut (.A(num[2]), .B(num[1]), .C(num[0]), .D(char[123]), 
         .Z(n1868)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[59:71])
    defparam i14590_2_lut_4_lut.init = 16'h8000;
    LUT4 cnt_init_4__I_0_333_i8_2_lut_rep_348_3_lut (.A(cnt_init[3]), .B(cnt_init[4]), 
         .C(cnt_init[2]), .Z(n29624)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(109[8:12])
    defparam cnt_init_4__I_0_333_i8_2_lut_rep_348_3_lut.init = 16'hfefe;
    LUT4 i21973_3_lut (.A(n2147), .B(n2525), .C(cnt_scan[0]), .Z(n28124)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i21973_3_lut.init = 16'hcaca;
    LUT4 i21972_3_lut (.A(n1391), .B(n1769), .C(cnt_scan[0]), .Z(n28123)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i21972_3_lut.init = 16'hcaca;
    LUT4 i22174_2_lut_rep_323_3_lut_4_lut (.A(cnt_init[3]), .B(cnt_init[4]), 
         .C(cnt_init[0]), .D(cnt_init[2]), .Z(n29599)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(109[8:12])
    defparam i22174_2_lut_rep_323_3_lut_4_lut.init = 16'h0001;
    LUT4 i1_3_lut_4_lut_adj_100 (.A(n29646), .B(cnt_init[0]), .C(oled_dcn_N_1613), 
         .D(state[4]), .Z(n15598)) /* synthesis lut_function=(!((B+!((D)+!C))+!A)) */ ;
    defparam i1_3_lut_4_lut_adj_100.init = 16'h2202;
    LUT4 mux_58_i1_4_lut (.A(n644), .B(cnt_scan[0]), .C(n29651), .D(n29611), 
         .Z(cnt_scan_4__N_1271[0])) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(130[16] 131[40])
    defparam mux_58_i1_4_lut.init = 16'h3a0a;
    LUT4 i22177_2_lut_rep_315_3_lut_4_lut (.A(cnt_init[3]), .B(cnt_init[4]), 
         .C(cnt_init[0]), .D(cnt_init[2]), .Z(n29591)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(109[8:12])
    defparam i22177_2_lut_rep_315_3_lut_4_lut.init = 16'h0010;
    LUT4 i3_4_lut_adj_101 (.A(num[6]), .B(num[5]), .C(n29615), .D(num[7]), 
         .Z(n644)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(128[11:14])
    defparam i3_4_lut_adj_101.init = 16'hfffe;
    FD1P3IX cnt_write_i0_i0 (.D(n13_adj_1713), .SP(sys_clk_c_enable_121), 
            .CD(n16617), .CK(sys_clk_c), .Q(cnt_write[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_write_i0_i0.GSR = "ENABLED";
    LUT4 i3_4_lut_adj_102 (.A(cnt_scan[0]), .B(cnt_scan[2]), .C(cnt_scan[4]), 
         .D(cnt_scan[1]), .Z(n15356)) /* synthesis lut_function=((B+(C+!(D)))+!A) */ ;
    defparam i3_4_lut_adj_102.init = 16'hfdff;
    LUT4 i1_4_lut_adj_103 (.A(n8851), .B(n29621), .C(n27977), .D(n29622), 
         .Z(n22719)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
    defparam i1_4_lut_adj_103.init = 16'h0040;
    CCU2D sub_1769_add_2_15 (.A0(cnt_delay[13]), .B0(num_delay[13]), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[14]), .B1(num_delay[14]), .C1(GND_net), 
          .D1(GND_net), .CIN(n24993), .COUT(n24994));
    defparam sub_1769_add_2_15.INIT0 = 16'h5999;
    defparam sub_1769_add_2_15.INIT1 = 16'h5999;
    defparam sub_1769_add_2_15.INJECT1_0 = "NO";
    defparam sub_1769_add_2_15.INJECT1_1 = "NO";
    CCU2D sub_1769_add_2_13 (.A0(cnt_delay[11]), .B0(num_delay[11]), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[12]), .B1(num_delay[12]), .C1(GND_net), 
          .D1(GND_net), .CIN(n24992), .COUT(n24993));
    defparam sub_1769_add_2_13.INIT0 = 16'h5999;
    defparam sub_1769_add_2_13.INIT1 = 16'h5999;
    defparam sub_1769_add_2_13.INJECT1_0 = "NO";
    defparam sub_1769_add_2_13.INJECT1_1 = "NO";
    LUT4 i2833_2_lut_3_lut_4_lut (.A(cnt_main[1]), .B(\cnt_main[0] ), .C(cnt_main[3]), 
         .D(cnt_main[2]), .Z(n8312)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(77[24:39])
    defparam i2833_2_lut_3_lut_4_lut.init = 16'h8000;
    LUT4 i2853_2_lut (.A(cnt_init[1]), .B(cnt_init[0]), .Z(n443[1])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(109[49:64])
    defparam i2853_2_lut.init = 16'h6666;
    LUT4 i92_4_lut_adj_104 (.A(n25083), .B(n1012), .C(cnt_scan[1]), .D(n29711), 
         .Z(n57_adj_1714)) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;
    defparam i92_4_lut_adj_104.init = 16'hca0a;
    LUT4 i2824_2_lut_3_lut (.A(cnt_main[1]), .B(\cnt_main[0] ), .C(cnt_main[2]), 
         .Z(n2[2])) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(77[24:39])
    defparam i2824_2_lut_3_lut.init = 16'h7878;
    CCU2D sub_1769_add_2_11 (.A0(cnt_delay[9]), .B0(num_delay[9]), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[10]), .B1(num_delay[10]), .C1(GND_net), 
          .D1(GND_net), .CIN(n24991), .COUT(n24992));
    defparam sub_1769_add_2_11.INIT0 = 16'h5999;
    defparam sub_1769_add_2_11.INIT1 = 16'h5999;
    defparam sub_1769_add_2_11.INJECT1_0 = "NO";
    defparam sub_1769_add_2_11.INJECT1_1 = "NO";
    LUT4 i1_4_lut_adj_105 (.A(state[0]), .B(num_delay[11]), .C(n16_adj_1716), 
         .D(n19), .Z(num_delay_15__N_1194[11])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_105.init = 16'hdc50;
    LUT4 i2826_2_lut_rep_340_3_lut (.A(cnt_main[1]), .B(\cnt_main[0] ), 
         .C(cnt_main[2]), .Z(n29616)) /* synthesis lut_function=(A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(77[24:39])
    defparam i2826_2_lut_rep_340_3_lut.init = 16'h8080;
    LUT4 mux_58_i2_4_lut (.A(n644), .B(n653[1]), .C(n29651), .D(n29611), 
         .Z(cnt_scan_4__N_1271[1])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(130[16] 131[40])
    defparam mux_58_i2_4_lut.init = 16'hca0a;
    LUT4 i2889_2_lut (.A(cnt_scan[1]), .B(cnt_scan[0]), .Z(n653[1])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(131[24:39])
    defparam i2889_2_lut.init = 16'h6666;
    FD1P3IX char_i0_i122 (.D(n25220), .SP(sys_clk_c_enable_95), .CD(n16601), 
            .CK(sys_clk_c), .Q(char[122])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam char_i0_i122.GSR = "ENABLED";
    LUT4 mux_58_i3_4_lut (.A(n644), .B(n653[2]), .C(n29651), .D(n29611), 
         .Z(cnt_scan_4__N_1271[2])) /* synthesis lut_function=(A (B (C (D)))+!A (B ((D)+!C)+!B !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(130[16] 131[40])
    defparam mux_58_i3_4_lut.init = 16'hc505;
    LUT4 i2_2_lut_rep_362_3_lut_4_lut (.A(cnt_init[3]), .B(cnt_init[4]), 
         .C(cnt_init[1]), .D(cnt_init[2]), .Z(n29638)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(109[8:12])
    defparam i2_2_lut_rep_362_3_lut_4_lut.init = 16'hfeff;
    FD1P3IX char_i0_i124 (.D(n27371), .SP(sys_clk_c_enable_95), .CD(n20524), 
            .CK(sys_clk_c), .Q(char[124])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam char_i0_i124.GSR = "ENABLED";
    LUT4 i22157_2_lut_4_lut (.A(n29555), .B(cnt_main[3]), .C(cnt_main[1]), 
         .D(cnt_main[2]), .Z(n27371)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;
    defparam i22157_2_lut_4_lut.init = 16'h0100;
    LUT4 i22011_3_lut (.A(\char_reg[1] ), .B(char_reg_c[0]), .C(cnt_write[1]), 
         .Z(n28162)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i22011_3_lut.init = 16'hcaca;
    LUT4 mux_58_i4_4_lut (.A(n644), .B(n653[3]), .C(n29651), .D(n29611), 
         .Z(cnt_scan_4__N_1271[3])) /* synthesis lut_function=(A (B (C (D)))+!A (B ((D)+!C)+!B !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(130[16] 131[40])
    defparam mux_58_i4_4_lut.init = 16'hc505;
    CCU2D sub_1769_add_2_9 (.A0(cnt_delay[7]), .B0(num_delay[7]), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[8]), .B1(num_delay[8]), .C1(GND_net), 
          .D1(GND_net), .CIN(n24990), .COUT(n24991));
    defparam sub_1769_add_2_9.INIT0 = 16'h5999;
    defparam sub_1769_add_2_9.INIT1 = 16'h5999;
    defparam sub_1769_add_2_9.INJECT1_0 = "NO";
    defparam sub_1769_add_2_9.INJECT1_1 = "NO";
    PFUMX i21966 (.BLUT(n28113), .ALUT(n28114), .C0(cnt_main[1]), .Z(n28117));
    LUT4 i2_3_lut_rep_371_4_lut (.A(cnt_init[3]), .B(cnt_init[4]), .C(cnt_init[0]), 
         .D(cnt_init[2]), .Z(n29647)) /* synthesis lut_function=(A+(B+(C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(109[8:12])
    defparam i2_3_lut_rep_371_4_lut.init = 16'hfeee;
    LUT4 i2_4_lut_adj_106 (.A(cnt_scan[4]), .B(n4_adj_1710), .C(n11_adj_1717), 
         .D(n8384), .Z(n27493)) /* synthesis lut_function=(!(A ((C+(D))+!B)+!A ((C+!(D))+!B))) */ ;
    defparam i2_4_lut_adj_106.init = 16'h0408;
    CCU2D sub_1769_add_2_7 (.A0(cnt_delay[5]), .B0(num_delay[5]), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[6]), .B1(num_delay[6]), .C1(GND_net), 
          .D1(GND_net), .CIN(n24989), .COUT(n24990));
    defparam sub_1769_add_2_7.INIT0 = 16'h5999;
    defparam sub_1769_add_2_7.INIT1 = 16'h5999;
    defparam sub_1769_add_2_7.INJECT1_0 = "NO";
    defparam sub_1769_add_2_7.INJECT1_1 = "NO";
    LUT4 i1_3_lut_4_lut_adj_107 (.A(n38), .B(n29625), .C(n5534), .D(n36_adj_1718), 
         .Z(sys_clk_c_enable_29)) /* synthesis lut_function=(A (B (C (D)))+!A (C (D))) */ ;
    defparam i1_3_lut_4_lut_adj_107.init = 16'hd000;
    LUT4 i9950_2_lut_rep_427 (.A(cnt_main[3]), .B(sign), .Z(n29703)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam i9950_2_lut_rep_427.init = 16'h8888;
    LUT4 i21846_2_lut_3_lut_4_lut (.A(cnt_main[3]), .B(sign), .C(cnt_main[1]), 
         .D(\cnt_main[0] ), .Z(n27994)) /* synthesis lut_function=(A (B+(C+(D)))+!A (C+(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam i21846_2_lut_3_lut_4_lut.init = 16'hfff8;
    LUT4 i14620_2_lut_rep_428 (.A(state[3]), .B(state[0]), .Z(n29704)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i14620_2_lut_rep_428.init = 16'heeee;
    LUT4 i22226_2_lut_4_lut_4_lut (.A(state[3]), .B(state[0]), .C(n29608), 
         .D(n12995), .Z(n16671)) /* synthesis lut_function=(!(A+!(B (C)+!B (C (D))))) */ ;
    defparam i22226_2_lut_4_lut_4_lut.init = 16'h5040;
    LUT4 i15163_3_lut_rep_277_4_lut (.A(state[3]), .B(state[0]), .C(n29608), 
         .D(n12995), .Z(sys_clk_c_enable_108)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (C (D)))) */ ;
    defparam i15163_3_lut_rep_277_4_lut.init = 16'hf0e0;
    LUT4 i30_4_lut_3_lut_rep_429 (.A(state[3]), .B(state[0]), .C(state[1]), 
         .Z(n29705)) /* synthesis lut_function=(!(A (B+(C))+!A (B (C)+!B !(C)))) */ ;
    defparam i30_4_lut_3_lut_rep_429.init = 16'h1616;
    LUT4 i1_2_lut_rep_318_4_lut (.A(state[3]), .B(state[0]), .C(state[1]), 
         .D(state[2]), .Z(n29594)) /* synthesis lut_function=(A (B+(C+(D)))+!A (B (C+(D))+!B ((D)+!C))) */ ;
    defparam i1_2_lut_rep_318_4_lut.init = 16'hffe9;
    FD1P3IX cnt_scan_i0_i0 (.D(cnt_scan_4__N_1271[0]), .SP(sys_clk_c_enable_106), 
            .CD(n16634), .CK(sys_clk_c), .Q(cnt_scan[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_scan_i0_i0.GSR = "ENABLED";
    CCU2D sub_1769_add_2_5 (.A0(cnt_delay[3]), .B0(num_delay[3]), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[4]), .B1(num_delay[4]), .C1(GND_net), 
          .D1(GND_net), .CIN(n24988), .COUT(n24989));
    defparam sub_1769_add_2_5.INIT0 = 16'h5999;
    defparam sub_1769_add_2_5.INIT1 = 16'h5999;
    defparam sub_1769_add_2_5.INJECT1_0 = "NO";
    defparam sub_1769_add_2_5.INJECT1_1 = "NO";
    LUT4 i22193_4_lut (.A(n8851), .B(n28258), .C(n18_adj_1719), .D(n27), 
         .Z(sys_clk_c_enable_100)) /* synthesis lut_function=(!(A+((C (D))+!B))) */ ;
    defparam i22193_4_lut.init = 16'h0444;
    LUT4 i39_4_lut (.A(n29637), .B(cnt_init[0]), .C(n29638), .D(n29622), 
         .Z(n18_adj_1719)) /* synthesis lut_function=(!(A+(B ((D)+!C)))) */ ;
    defparam i39_4_lut.init = 16'h1151;
    LUT4 i3_4_lut_adj_108 (.A(n29037), .B(n29591), .C(n29599), .D(cnt_init[1]), 
         .Z(n27500)) /* synthesis lut_function=(!((B (C+!(D))+!B (C (D)))+!A)) */ ;
    defparam i3_4_lut_adj_108.init = 16'h0a22;
    PFUMX i22557 (.BLUT(n29142), .ALUT(n29141), .C0(num[3]), .Z(n2131));
    LUT4 i2927_2_lut_rep_431 (.A(cnt_write[1]), .B(cnt_write[0]), .Z(n29707)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(152[25:41])
    defparam i2927_2_lut_rep_431.init = 16'h8888;
    LUT4 i2939_2_lut_3_lut_4_lut (.A(cnt_write[1]), .B(cnt_write[0]), .C(cnt_write[3]), 
         .D(cnt_write[2]), .Z(n2582[3])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(152[25:41])
    defparam i2939_2_lut_3_lut_4_lut.init = 16'h78f0;
    LUT4 i2932_2_lut_3_lut (.A(cnt_write[1]), .B(cnt_write[0]), .C(cnt_write[2]), 
         .Z(n2582[2])) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(152[25:41])
    defparam i2932_2_lut_3_lut.init = 16'h7878;
    LUT4 i1_4_lut_adj_109 (.A(cnt_init[0]), .B(num_delay[10]), .C(n29580), 
         .D(n29647), .Z(num_delay_15__N_1505[10])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D)))) */ ;
    defparam i1_4_lut_adj_109.init = 16'hcc40;
    LUT4 n29395_bdd_3_lut_else_4_lut (.A(cnt[3]), .B(\cnt[1] ), .C(\cnt[2] ), 
         .D(cnt[4]), .Z(n29717)) /* synthesis lut_function=(!(A (B (D)+!B (C (D)+!C !(D)))+!A !(B (C)+!B (D)))) */ ;
    defparam n29395_bdd_3_lut_else_4_lut.init = 16'h53e8;
    CCU2D sub_1769_add_2_3 (.A0(cnt_delay[1]), .B0(num_delay[1]), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[2]), .B1(num_delay[2]), .C1(GND_net), 
          .D1(GND_net), .CIN(n24987), .COUT(n24988));
    defparam sub_1769_add_2_3.INIT0 = 16'h5999;
    defparam sub_1769_add_2_3.INIT1 = 16'h5999;
    defparam sub_1769_add_2_3.INJECT1_0 = "NO";
    defparam sub_1769_add_2_3.INJECT1_1 = "NO";
    LUT4 i5_4_lut (.A(n29728), .B(n29576), .C(n29671), .D(n29622), .Z(n27643)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;
    defparam i5_4_lut.init = 16'h0008;
    CCU2D sub_1769_add_2_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[0]), .B1(num_delay[0]), .C1(GND_net), 
          .D1(GND_net), .COUT(n24987));
    defparam sub_1769_add_2_1.INIT0 = 16'h0000;
    defparam sub_1769_add_2_1.INIT1 = 16'h5999;
    defparam sub_1769_add_2_1.INJECT1_0 = "NO";
    defparam sub_1769_add_2_1.INJECT1_1 = "NO";
    LUT4 i1_2_lut_3_lut_3_lut_4_lut_4_lut (.A(cnt_main[3]), .B(n29567), 
         .C(n28119), .D(cnt_main[4]), .Z(n27668)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;
    defparam i1_2_lut_3_lut_3_lut_4_lut_4_lut.init = 16'h0080;
    LUT4 i1_2_lut_3_lut_3_lut_4_lut_4_lut_adj_110 (.A(cnt_main[3]), .B(n29567), 
         .C(n28112), .D(cnt_main[4]), .Z(n27667)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;
    defparam i1_2_lut_3_lut_3_lut_4_lut_4_lut_adj_110.init = 16'h0080;
    LUT4 n29522_bdd_2_lut_4_lut (.A(n29521), .B(n14), .C(state[5]), .D(state[3]), 
         .Z(n29523)) /* synthesis lut_function=(!(A (B (D)+!B (C+(D)))+!A (((D)+!C)+!B))) */ ;
    defparam n29522_bdd_2_lut_4_lut.init = 16'h00ca;
    LUT4 i2_4_lut_4_lut_adj_111 (.A(cnt_main[3]), .B(cnt_main[4]), .C(n27909), 
         .D(sign), .Z(n10)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;
    defparam i2_4_lut_4_lut_adj_111.init = 16'h0002;
    LUT4 i33_4_lut_adj_112 (.A(num_delay[11]), .B(num_delay_15__N_1505[11]), 
         .C(state[2]), .D(n20968), .Z(n16_adj_1716)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_112.init = 16'h0aca;
    CCU2D add_100_17 (.A0(cnt_delay[15]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n24959), .S0(n2606[15]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(178[29:45])
    defparam add_100_17.INIT0 = 16'h5aaa;
    defparam add_100_17.INIT1 = 16'h0000;
    defparam add_100_17.INJECT1_0 = "NO";
    defparam add_100_17.INJECT1_1 = "NO";
    CCU2D add_100_15 (.A0(cnt_delay[13]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[14]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24958), .COUT(n24959), .S0(n2606[13]), 
          .S1(n2606[14]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(178[29:45])
    defparam add_100_15.INIT0 = 16'h5aaa;
    defparam add_100_15.INIT1 = 16'h5aaa;
    defparam add_100_15.INJECT1_0 = "NO";
    defparam add_100_15.INJECT1_1 = "NO";
    LUT4 i21829_2_lut_3_lut_4_lut (.A(cnt_init[0]), .B(n29638), .C(n29622), 
         .D(n29637), .Z(n27977)) /* synthesis lut_function=(A ((C+(D))+!B)+!A (C+(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[7] 124[14])
    defparam i21829_2_lut_3_lut_4_lut.init = 16'hfff2;
    LUT4 i1_4_lut_adj_113 (.A(cnt_init[0]), .B(num_delay[11]), .C(n29580), 
         .D(n29647), .Z(num_delay_15__N_1505[11])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D)))) */ ;
    defparam i1_4_lut_adj_113.init = 16'hcc40;
    LUT4 i1_3_lut_rep_305_4_lut_4_lut (.A(cnt_init[0]), .B(n29624), .C(oled_dcn_N_1613), 
         .D(n29646), .Z(n29581)) /* synthesis lut_function=(!(A+!((C (D))+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i1_3_lut_rep_305_4_lut_4_lut.init = 16'h5111;
    FD1P3IX cnt_init_i0_i1 (.D(n443[1]), .SP(sys_clk_c_enable_100), .CD(n22719), 
            .CK(sys_clk_c), .Q(cnt_init[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_init_i0_i1.GSR = "ENABLED";
    LUT4 i1_2_lut_2_lut_adj_114 (.A(cnt_init[0]), .B(state[0]), .Z(n4_c)) /* synthesis lut_function=(!(A+!(B))) */ ;
    defparam i1_2_lut_2_lut_adj_114.init = 16'h4444;
    LUT4 i1_2_lut_4_lut_4_lut_adj_115 (.A(cnt_init[0]), .B(oled_dcn_N_1613), 
         .C(n29701), .D(n29646), .Z(n6_adj_1676)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (C)))) */ ;
    defparam i1_2_lut_4_lut_4_lut_adj_115.init = 16'h5450;
    LUT4 i1_4_lut_4_lut_adj_116 (.A(cnt_init[0]), .B(n27792), .C(n19_adj_1705), 
         .D(state[2]), .Z(n6_adj_1720)) /* synthesis lut_function=(A (C (D))+!A (B (D)+!B (C (D)))) */ ;
    defparam i1_4_lut_4_lut_adj_116.init = 16'hf400;
    LUT4 i1_4_lut_4_lut_adj_117 (.A(cnt_init[0]), .B(n27794), .C(n19_adj_1704), 
         .D(state[2]), .Z(n6_adj_1721)) /* synthesis lut_function=(A (C (D))+!A (B (D)+!B (C (D)))) */ ;
    defparam i1_4_lut_4_lut_adj_117.init = 16'hf400;
    LUT4 i1_4_lut_4_lut_adj_118 (.A(cnt_init[0]), .B(n27796), .C(n19_adj_1706), 
         .D(state[2]), .Z(n6_adj_1722)) /* synthesis lut_function=(A (C (D))+!A (B (D)+!B (C (D)))) */ ;
    defparam i1_4_lut_4_lut_adj_118.init = 16'hf400;
    FD1P3IX cnt_init_i0_i2 (.D(n443[2]), .SP(sys_clk_c_enable_100), .CD(n22719), 
            .CK(sys_clk_c), .Q(cnt_init[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_init_i0_i2.GSR = "ENABLED";
    LUT4 i21962_3_lut (.A(sign), .B(temp_h[2]), .C(\cnt_main[0] ), .Z(n28113)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i21962_3_lut.init = 16'hcaca;
    LUT4 n1015_bdd_4_lut_22832 (.A(n1015), .B(cnt_scan[0]), .C(cnt_scan[2]), 
         .D(x_ph[2]), .Z(n29452)) /* synthesis lut_function=(A (B (C)+!B !(C+!(D)))+!A !(B+(C+!(D)))) */ ;
    defparam n1015_bdd_4_lut_22832.init = 16'h8380;
    FD1P3IX cnt_init_i0_i3 (.D(n443[3]), .SP(sys_clk_c_enable_100), .CD(n22719), 
            .CK(sys_clk_c), .Q(cnt_init[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_init_i0_i3.GSR = "ENABLED";
    LUT4 n1676_bdd_2_lut_22405_3_lut (.A(n2130), .B(num[4]), .C(n28763), 
         .Z(n28764)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[51:79])
    defparam n1676_bdd_2_lut_22405_3_lut.init = 16'h2020;
    PFUMX i22785 (.BLUT(n29717), .ALUT(n29718), .C0(\cnt[0] ), .Z(n29719));
    LUT4 i1_2_lut_4_lut_4_lut_adj_119 (.A(state[1]), .B(oled_dcn_N_1613), 
         .C(n29599), .D(n29593), .Z(n17)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i1_2_lut_4_lut_4_lut_adj_119.init = 16'h5450;
    FD1P3IX cnt_init_i0_i4 (.D(n443[4]), .SP(sys_clk_c_enable_100), .CD(n22719), 
            .CK(sys_clk_c), .Q(cnt_init[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_init_i0_i4.GSR = "ENABLED";
    LUT4 i1_4_lut_4_lut_4_lut (.A(state[1]), .B(n15598), .C(n6_adj_1723), 
         .D(state[3]), .Z(n9_adj_1724)) /* synthesis lut_function=(!(A+(B (D)+!B ((D)+!C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i1_4_lut_4_lut_4_lut.init = 16'h0054;
    LUT4 i1_2_lut_2_lut_adj_120 (.A(state[1]), .B(state[3]), .Z(n4_adj_1725)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i1_2_lut_2_lut_adj_120.init = 16'h4444;
    LUT4 i1_3_lut_3_lut_adj_121 (.A(state[1]), .B(n29581), .C(state[3]), 
         .Z(n12_adj_1726)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i1_3_lut_3_lut_adj_121.init = 16'h4040;
    LUT4 i92_4_lut_4_lut (.A(cnt_scan[2]), .B(n28125), .C(cnt_scan[3]), 
         .D(n25083), .Z(n57_adj_1727)) /* synthesis lut_function=(!(A (C+!(D))+!A !(B (C+(D))+!B !(C+!(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(146[8:13])
    defparam i92_4_lut_4_lut.init = 16'h4f40;
    LUT4 n1676_bdd_2_lut_22709_2_lut (.A(cnt_scan[2]), .B(n29382), .Z(n29383)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(146[8:13])
    defparam n1676_bdd_2_lut_22709_2_lut.init = 16'h4444;
    LUT4 n1676_bdd_2_lut_22747_2_lut (.A(cnt_scan[2]), .B(n29450), .Z(n29451)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(146[8:13])
    defparam n1676_bdd_2_lut_22747_2_lut.init = 16'h4444;
    LUT4 i21963_3_lut (.A(temp_l[2]), .B(temp_p[2]), .C(\cnt_main[0] ), 
         .Z(n28114)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i21963_3_lut.init = 16'hcaca;
    LUT4 i1_2_lut_2_lut_adj_122 (.A(cnt_scan[2]), .B(n29278), .Z(n61)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(146[8:13])
    defparam i1_2_lut_2_lut_adj_122.init = 16'h4444;
    FD1P3IX cnt_delay_i0_i1 (.D(n2606[1]), .SP(sys_clk_c_enable_131), .CD(n16582), 
            .CK(sys_clk_c), .Q(cnt_delay[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_delay_i0_i1.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i2 (.D(n2606[2]), .SP(sys_clk_c_enable_131), .CD(n16582), 
            .CK(sys_clk_c), .Q(cnt_delay[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_delay_i0_i2.GSR = "ENABLED";
    FD1P3IX cnt_scan_i0_i1 (.D(cnt_scan_4__N_1271[1]), .SP(sys_clk_c_enable_106), 
            .CD(n16634), .CK(sys_clk_c), .Q(cnt_scan[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_scan_i0_i1.GSR = "ENABLED";
    FD1P3IX cnt_scan_i0_i2 (.D(cnt_scan_4__N_1271[2]), .SP(sys_clk_c_enable_106), 
            .CD(n16634), .CK(sys_clk_c), .Q(cnt_scan[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_scan_i0_i2.GSR = "ENABLED";
    FD1P3IX cnt_scan_i0_i3 (.D(cnt_scan_4__N_1271[3]), .SP(sys_clk_c_enable_106), 
            .CD(n16634), .CK(sys_clk_c), .Q(cnt_scan[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_scan_i0_i3.GSR = "ENABLED";
    FD1P3AX cnt_scan_i0_i4 (.D(n27493), .SP(sys_clk_c_enable_106), .CK(sys_clk_c), 
            .Q(cnt_scan[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_scan_i0_i4.GSR = "ENABLED";
    LUT4 i22160_4_lut (.A(n29567), .B(n29574), .C(n28022), .D(n27835), 
         .Z(n28226)) /* synthesis lut_function=(!(A (B+!(C+(D))))) */ ;
    defparam i22160_4_lut.init = 16'h7775;
    LUT4 n1676_bdd_2_lut_22718_2_lut (.A(cnt_scan[2]), .B(n29388), .Z(n29389)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(146[8:13])
    defparam n1676_bdd_2_lut_22718_2_lut.init = 16'h4444;
    LUT4 i1_2_lut_3_lut_adj_123 (.A(cnt_scan[2]), .B(cnt_scan[0]), .C(y_p[4]), 
         .Z(n25083)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;
    defparam i1_2_lut_3_lut_adj_123.init = 16'h1010;
    LUT4 i21692_2_lut (.A(cnt_main[4]), .B(cnt_main[2]), .Z(n27835)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i21692_2_lut.init = 16'heeee;
    LUT4 i1_2_lut_rep_435 (.A(cnt_scan[0]), .B(cnt_scan[2]), .Z(n29711)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_rep_435.init = 16'h8888;
    LUT4 i1_4_lut_adj_124 (.A(n29616), .B(n29555), .C(n28172), .D(cnt_main[3]), 
         .Z(n27671)) /* synthesis lut_function=(!(A (B+!(C+!(D)))+!A (B+!(C (D))))) */ ;
    defparam i1_4_lut_adj_124.init = 16'h3022;
    LUT4 i1_3_lut_3_lut_adj_125 (.A(state[2]), .B(n2796), .C(state_back[3]), 
         .Z(n12_adj_1728)) /* synthesis lut_function=(!(A+!((C)+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(107[5:9])
    defparam i1_3_lut_3_lut_adj_125.init = 16'h5151;
    LUT4 i1_2_lut_3_lut_3_lut (.A(state[2]), .B(state_back[0]), .C(n2796), 
         .Z(n27590)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(107[5:9])
    defparam i1_2_lut_3_lut_3_lut.init = 16'h4040;
    LUT4 i1_4_lut_adj_126 (.A(n24), .B(char_reg_c[0]), .C(n29625), .D(n27_adj_1729), 
         .Z(char_reg_7__N_1166[0])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_126.init = 16'hce0a;
    LUT4 i1_4_lut_4_lut_adj_127 (.A(state[2]), .B(n2796), .C(n29425), 
         .D(char_reg[7]), .Z(n12_adj_1730)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(107[5:9])
    defparam i1_4_lut_4_lut_adj_127.init = 16'h5450;
    LUT4 i1_4_lut_adj_128 (.A(n29616), .B(n29555), .C(n28122), .D(cnt_main[3]), 
         .Z(n27673)) /* synthesis lut_function=(!(A (B+!(C+!(D)))+!A (B+!(C (D))))) */ ;
    defparam i1_4_lut_adj_128.init = 16'h3022;
    LUT4 i1_4_lut_adj_129 (.A(n27527), .B(n27407), .C(state[0]), .D(n29632), 
         .Z(sys_clk_c_enable_9)) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C (D)))) */ ;
    defparam i1_4_lut_adj_129.init = 16'hc088;
    LUT4 i1_3_lut_adj_130 (.A(state[4]), .B(cnt_write[1]), .C(n28696), 
         .Z(n27527)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;
    defparam i1_3_lut_adj_130.init = 16'h2020;
    LUT4 mux_1614_i1_4_lut (.A(oled_csn_N_1597), .B(state[0]), .C(n29632), 
         .D(state[4]), .Z(n5456[0])) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam mux_1614_i1_4_lut.init = 16'hcac0;
    LUT4 i3_4_lut_adj_131 (.A(n29596), .B(n29682), .C(n29681), .D(n27907), 
         .Z(n27407)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;
    defparam i3_4_lut_adj_131.init = 16'h0010;
    LUT4 i1_4_lut_4_lut_adj_132 (.A(state[2]), .B(n2796), .C(n29386), 
         .D(\char_reg[1] ), .Z(n12_adj_1731)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(107[5:9])
    defparam i1_4_lut_4_lut_adj_132.init = 16'h5450;
    CCU2D add_100_13 (.A0(cnt_delay[11]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_delay[12]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24957), .COUT(n24958), .S0(n2606[11]), 
          .S1(n2606[12]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(178[29:45])
    defparam add_100_13.INIT0 = 16'h5aaa;
    defparam add_100_13.INIT1 = 16'h5aaa;
    defparam add_100_13.INJECT1_0 = "NO";
    defparam add_100_13.INJECT1_1 = "NO";
    LUT4 i21762_2_lut (.A(state[1]), .B(state[5]), .Z(n27907)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i21762_2_lut.init = 16'heeee;
    LUT4 i24_2_lut (.A(state[2]), .B(state[3]), .Z(n38)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i24_2_lut.init = 16'h6666;
    LUT4 i1_4_lut_adj_133 (.A(n5534), .B(n7507), .C(n16530), .D(n29596), 
         .Z(sys_clk_c_enable_10)) /* synthesis lut_function=(!((B (C (D))+!B (C+!(D)))+!A)) */ ;
    defparam i1_4_lut_adj_133.init = 16'h0a88;
    LUT4 i24_4_lut (.A(cnt_scan[4]), .B(n29576), .C(state[2]), .D(n18_adj_1689), 
         .Z(n16530)) /* synthesis lut_function=(A (B+!(C))+!A (B (C+(D))+!B !(C+!(D)))) */ ;
    defparam i24_4_lut.init = 16'hcfca;
    LUT4 i1_2_lut_3_lut_3_lut_adj_134 (.A(state[2]), .B(state_back[2]), 
         .C(n2796), .Z(n27589)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(107[5:9])
    defparam i1_2_lut_3_lut_3_lut_adj_134.init = 16'h4040;
    LUT4 i1_4_lut_4_lut_adj_135 (.A(state[2]), .B(n2796), .C(n64_adj_1668), 
         .D(\char_reg[2] ), .Z(n12_adj_1732)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(107[5:9])
    defparam i1_4_lut_4_lut_adj_135.init = 16'h5450;
    LUT4 i1_4_lut_4_lut_adj_136 (.A(state[2]), .B(n2796), .C(n29392), 
         .D(char_reg_c[0]), .Z(n12_adj_1733)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(107[5:9])
    defparam i1_4_lut_4_lut_adj_136.init = 16'h5450;
    LUT4 i1_4_lut_4_lut_adj_137 (.A(state[2]), .B(n2796), .C(n64_adj_1669), 
         .D(\char_reg[3] ), .Z(n12_adj_1734)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(107[5:9])
    defparam i1_4_lut_4_lut_adj_137.init = 16'h5450;
    CCU2D add_100_11 (.A0(cnt_delay[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_delay[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n24956), .COUT(n24957), .S0(n2606[9]), .S1(n2606[10]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(178[29:45])
    defparam add_100_11.INIT0 = 16'h5aaa;
    defparam add_100_11.INIT1 = 16'h5aaa;
    defparam add_100_11.INJECT1_0 = "NO";
    defparam add_100_11.INJECT1_1 = "NO";
    LUT4 i3_4_lut_adj_138 (.A(cnt_scan[4]), .B(n29596), .C(state[2]), 
         .D(n27_adj_1735), .Z(n27149)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;
    defparam i3_4_lut_adj_138.init = 16'h0400;
    LUT4 i1_3_lut_adj_139 (.A(cnt_scan[3]), .B(cnt_scan[2]), .Z(n27_adj_1735)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i1_3_lut_adj_139.init = 16'h6666;
    LUT4 i1_4_lut_4_lut_adj_140 (.A(state[2]), .B(n2796), .C(n64), .D(char_reg_c[4]), 
         .Z(n12_adj_1736)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(107[5:9])
    defparam i1_4_lut_4_lut_adj_140.init = 16'h5450;
    LUT4 i1_4_lut_4_lut_adj_141 (.A(state[2]), .B(n2796), .C(n64_adj_1667), 
         .D(char_reg_c[5]), .Z(n12_adj_1737)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(107[5:9])
    defparam i1_4_lut_4_lut_adj_141.init = 16'h5450;
    LUT4 i1_4_lut_adj_142 (.A(state[1]), .B(n29726), .C(n27797), .D(state[5]), 
         .Z(n5534)) /* synthesis lut_function=(A (B+!(C+(D)))+!A (B+!(C+!(D)))) */ ;
    defparam i1_4_lut_adj_142.init = 16'hcdce;
    LUT4 i1_2_lut_3_lut_3_lut_adj_143 (.A(state[2]), .B(state_back[4]), 
         .C(n2796), .Z(n27592)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(107[5:9])
    defparam i1_2_lut_3_lut_3_lut_adj_143.init = 16'h4040;
    LUT4 i1_4_lut_4_lut_adj_144 (.A(state[2]), .B(n2796), .C(n30756), 
         .D(char_reg[6]), .Z(n12_adj_1738)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(107[5:9])
    defparam i1_4_lut_4_lut_adj_144.init = 16'h5450;
    LUT4 i1_4_lut_adj_145 (.A(n24_adj_1739), .B(state_back[0]), .C(n29625), 
         .D(n27_adj_1729), .Z(state_back_5__N_1248[0])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_145.init = 16'hce0a;
    LUT4 i1_2_lut_3_lut_3_lut_adj_146 (.A(state[2]), .B(state_back[5]), 
         .C(n2796), .Z(n27591)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(107[5:9])
    defparam i1_2_lut_3_lut_3_lut_adj_146.init = 16'h4040;
    LUT4 i22195_4_lut (.A(state[0]), .B(num_delay[0]), .C(n21163), .D(n19), 
         .Z(num_delay_15__N_1194[0])) /* synthesis lut_function=(A (B+!(D))+!A (B (C)+!B !((D)+!C))) */ ;
    defparam i22195_4_lut.init = 16'hc8fa;
    LUT4 i41_4_lut (.A(num_delay[0]), .B(n20968), .C(state[2]), .D(n27472), 
         .Z(n21163)) /* synthesis lut_function=(A (B+((D)+!C))+!A (B (C)+!B (C (D)))) */ ;
    defparam i41_4_lut.init = 16'hfaca;
    LUT4 i1_4_lut_adj_147 (.A(cnt_init[0]), .B(num_delay[0]), .C(n15_adj_1740), 
         .D(n29647), .Z(n27472)) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_147.init = 16'hdc50;
    LUT4 i1_4_lut_adj_148 (.A(num_delay[0]), .B(n29701), .C(n29646), .D(oled_dcn_N_1613), 
         .Z(n15_adj_1740)) /* synthesis lut_function=(A (B+(C))+!A !((D)+!C)) */ ;
    defparam i1_4_lut_adj_148.init = 16'ha8f8;
    LUT4 equal_1328_i7_2_lut_rep_436 (.A(state[4]), .B(state[5]), .Z(n29712)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(67[5:9])
    defparam equal_1328_i7_2_lut_rep_436.init = 16'heeee;
    LUT4 i1_2_lut_rep_376_3_lut (.A(state[4]), .B(state[5]), .C(state[1]), 
         .Z(n29652)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(67[5:9])
    defparam i1_2_lut_rep_376_3_lut.init = 16'hfefe;
    LUT4 num_3__bdd_4_lut (.A(char[2]), .B(num[2]), .C(num[1]), .D(num[0]), 
         .Z(n29142)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;
    defparam num_3__bdd_4_lut.init = 16'h0002;
    LUT4 num_3__bdd_4_lut_22556 (.A(char[122]), .B(num[2]), .C(num[1]), 
         .D(num[0]), .Z(n29141)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam num_3__bdd_4_lut_22556.init = 16'h8000;
    LUT4 i2_3_lut_rep_332_4_lut (.A(state[4]), .B(state[5]), .C(n29705), 
         .D(state[2]), .Z(n29608)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(67[5:9])
    defparam i2_3_lut_rep_332_4_lut.init = 16'h0010;
    LUT4 i1_4_lut_adj_149 (.A(state[0]), .B(num_delay[10]), .C(n16_adj_1741), 
         .D(n19), .Z(num_delay_15__N_1194[10])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_149.init = 16'hdc50;
    LUT4 i33_4_lut_adj_150 (.A(num_delay[10]), .B(num_delay_15__N_1505[10]), 
         .C(state[2]), .D(n20968), .Z(n16_adj_1741)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_150.init = 16'h0aca;
    LUT4 i7285_3_lut_4_lut_4_lut (.A(n29623), .B(n29590), .C(cnt_main[4]), 
         .D(n29703), .Z(n12995)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+(D)))+!A (B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam i7285_3_lut_4_lut_4_lut.init = 16'h3f35;
    LUT4 i1_4_lut_adj_151 (.A(n29616), .B(n29555), .C(n28973), .D(cnt_main[3]), 
         .Z(n27670)) /* synthesis lut_function=(!(A (B+!(C+!(D)))+!A (B+!(C (D))))) */ ;
    defparam i1_4_lut_adj_151.init = 16'h3022;
    LUT4 i1_2_lut_3_lut_4_lut_adj_152 (.A(state[4]), .B(state[5]), .C(state[3]), 
         .D(state[1]), .Z(n20968)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(67[5:9])
    defparam i1_2_lut_3_lut_4_lut_adj_152.init = 16'hfffe;
    LUT4 i22251_2_lut_4_lut (.A(state[2]), .B(n29705), .C(n29712), .D(n29740), 
         .Z(sys_clk_c_enable_92)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;
    defparam i22251_2_lut_4_lut.init = 16'h0400;
    LUT4 i14798_4_lut (.A(n29630), .B(n29567), .C(cnt_main[4]), .D(cnt_main[3]), 
         .Z(n6420[21])) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C))) */ ;
    defparam i14798_4_lut.init = 16'hc0c8;
    LUT4 equal_1322_i10_2_lut_rep_346_3_lut (.A(state[4]), .B(state[5]), 
         .C(state[3]), .Z(n29622)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(67[5:9])
    defparam equal_1322_i10_2_lut_rep_346_3_lut.init = 16'hfefe;
    LUT4 i1_4_lut_adj_153 (.A(state[0]), .B(num_delay[3]), .C(n16_adj_1742), 
         .D(n19), .Z(num_delay_15__N_1194[3])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_153.init = 16'hdc50;
    CCU2D add_100_9 (.A0(cnt_delay[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_delay[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n24955), .COUT(n24956), .S0(n2606[7]), .S1(n2606[8]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(178[29:45])
    defparam add_100_9.INIT0 = 16'h5aaa;
    defparam add_100_9.INIT1 = 16'h5aaa;
    defparam add_100_9.INJECT1_0 = "NO";
    defparam add_100_9.INJECT1_1 = "NO";
    LUT4 i33_4_lut_adj_154 (.A(num_delay[3]), .B(num_delay_15__N_1505[3]), 
         .C(state[2]), .D(n20968), .Z(n16_adj_1742)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_154.init = 16'h0aca;
    LUT4 num_2277_mux_6_i5_4_lut (.A(n29683), .B(n37[4]), .C(state[3]), 
         .D(n4_adj_1697), .Z(n1[4])) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;
    defparam num_2277_mux_6_i5_4_lut.init = 16'hcac0;
    LUT4 i1_4_lut_adj_155 (.A(n27407), .B(n27624), .C(state[0]), .D(n29632), 
         .Z(sys_clk_c_enable_17)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))) */ ;
    defparam i1_4_lut_adj_155.init = 16'ha088;
    LUT4 i1_4_lut_adj_156 (.A(n29591), .B(num_delay[3]), .C(n16_adj_1744), 
         .D(n29647), .Z(num_delay_15__N_1505[3])) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_156.init = 16'hfefa;
    LUT4 i1_3_lut_adj_157 (.A(state[4]), .B(oled_dat_N_1635), .C(n29632), 
         .Z(n27495)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;
    defparam i1_3_lut_adj_157.init = 16'h0808;
    LUT4 i1_3_lut_adj_158 (.A(cnt_init[0]), .B(num_delay[3]), .C(n29580), 
         .Z(n16_adj_1744)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
    defparam i1_3_lut_adj_158.init = 16'h4040;
    PFUMX i23369 (.BLUT(n30821), .ALUT(n30819), .C0(cnt_scan[3]), .Z(n30822));
    PFUMX i21967 (.BLUT(n28115), .ALUT(n28116), .C0(cnt_main[1]), .Z(n28118));
    PFUMX i23367 (.BLUT(n30817), .ALUT(n30816), .C0(cnt_scan[0]), .Z(n30818));
    CCU2D add_100_7 (.A0(cnt_delay[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_delay[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n24954), .COUT(n24955), .S0(n2606[5]), .S1(n2606[6]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(178[29:45])
    defparam add_100_7.INIT0 = 16'h5aaa;
    defparam add_100_7.INIT1 = 16'h5aaa;
    defparam add_100_7.INJECT1_0 = "NO";
    defparam add_100_7.INJECT1_1 = "NO";
    LUT4 i22269_4_lut (.A(n27411), .B(n29622), .C(n29665), .D(state[0]), 
         .Z(sys_clk_c_enable_122)) /* synthesis lut_function=(A+!(B+!(C (D)))) */ ;
    defparam i22269_4_lut.init = 16'hbaaa;
    LUT4 i3_4_lut_adj_159 (.A(n20968), .B(n29593), .C(state[0]), .D(state[2]), 
         .Z(n27411)) /* synthesis lut_function=(!(A+((C (D)+!C !(D))+!B))) */ ;
    defparam i3_4_lut_adj_159.init = 16'h0440;
    LUT4 i14735_2_lut (.A(n479[15]), .B(oled_dcn_N_1613), .Z(n505[15])) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam i14735_2_lut.init = 16'h2222;
    LUT4 i1_4_lut_adj_160 (.A(state[0]), .B(num_delay[9]), .C(n16_adj_1745), 
         .D(n19), .Z(num_delay_15__N_1194[9])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_160.init = 16'hdc50;
    LUT4 i14429_2_lut_3_lut (.A(cnt_scan[4]), .B(n29650), .C(state[2]), 
         .Z(n24_adj_1746)) /* synthesis lut_function=(!(A+(B+(C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(145[8:13])
    defparam i14429_2_lut_3_lut.init = 16'h0101;
    PFUMX i23350 (.BLUT(n30782), .ALUT(n30781), .C0(\cnt[1] ), .Z(n30783));
    LUT4 n1677_bdd_2_lut_22500_3_lut_4_lut (.A(cnt_scan[4]), .B(n29650), 
         .C(n29670), .D(n28941), .Z(n28943)) /* synthesis lut_function=(A ((D)+!C)+!A (((D)+!C)+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(145[8:13])
    defparam n1677_bdd_2_lut_22500_3_lut_4_lut.init = 16'hff1f;
    LUT4 i10527_2_lut_3_lut (.A(n21361), .B(n29547), .C(\cnt_main[0] ), 
         .Z(n16601)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i10527_2_lut_3_lut.init = 16'h8080;
    LUT4 oled_csn_N_1597_bdd_4_lut (.A(oled_csn_N_1597), .B(cnt_write[0]), 
         .C(cnt_write[2]), .D(cnt_write[3]), .Z(n28696)) /* synthesis lut_function=(!(A ((C+(D))+!B)+!A (B+(C+(D))))) */ ;
    defparam oled_csn_N_1597_bdd_4_lut.init = 16'h0009;
    LUT4 i33_4_lut_adj_161 (.A(num_delay[9]), .B(num_delay_15__N_1505[9]), 
         .C(state[2]), .D(n20968), .Z(n16_adj_1745)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_161.init = 16'h0aca;
    LUT4 i2_4_lut_4_lut_adj_162 (.A(cnt_scan[4]), .B(n29650), .C(n25417), 
         .D(n4_adj_1725), .Z(n5)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(145[8:13])
    defparam i2_4_lut_4_lut_adj_162.init = 16'h0400;
    LUT4 i1_2_lut_4_lut_adj_163 (.A(state[2]), .B(n29652), .C(state[0]), 
         .D(state[3]), .Z(n19)) /* synthesis lut_function=(A (B+(C+(D)))+!A (B+(D))) */ ;
    defparam i1_2_lut_4_lut_adj_163.init = 16'hffec;
    LUT4 i1_4_lut_4_lut_adj_164 (.A(state[2]), .B(n29652), .C(state[0]), 
         .D(state[3]), .Z(n27_adj_1729)) /* synthesis lut_function=(A (B+(C+(D)))+!A (B+(C (D)+!C !(D)))) */ ;
    defparam i1_4_lut_4_lut_adj_164.init = 16'hfeed;
    LUT4 cnt_3__bdd_4_lut (.A(cnt[3]), .B(\cnt[0] ), .C(\cnt[2] ), .D(\cnt[1] ), 
         .Z(n28720)) /* synthesis lut_function=(!(A (B (C)+!B (C+!(D)))+!A (B+!(C (D)+!C !(D))))) */ ;
    defparam cnt_3__bdd_4_lut.init = 16'h1a09;
    LUT4 i22184_4_lut (.A(n50), .B(n28249), .C(n29671), .D(n29682), 
         .Z(n42_adj_1683)) /* synthesis lut_function=(A (B (C+(D)))+!A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i22184_4_lut.init = 16'hccc4;
    LUT4 i22183_4_lut (.A(n45_adj_1747), .B(n29712), .C(n47_adj_1748), 
         .D(n29671), .Z(n28249)) /* synthesis lut_function=(A (B)+!A (B+((D)+!C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i22183_4_lut.init = 16'hddcd;
    PFUMX i23335 (.BLUT(n30751), .ALUT(n30750), .C0(cnt_scan[2]), .Z(n30752));
    LUT4 i2_4_lut_adj_165 (.A(state[0]), .B(n29682), .C(state_5__N_1553[0]), 
         .D(state[1]), .Z(n45_adj_1747)) /* synthesis lut_function=(!(A (B+(D))+!A (B+(C+!(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i2_4_lut_adj_165.init = 16'h0122;
    LUT4 mux_14_Mux_0_i31_4_lut (.A(state[0]), .B(n29590), .C(cnt_main[4]), 
         .D(n29568), .Z(state_5__N_1553[0])) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam mux_14_Mux_0_i31_4_lut.init = 16'hc0ca;
    LUT4 i2_3_lut_rep_337 (.A(num[3]), .B(char[124]), .C(n29653), .Z(n29613)) /* synthesis lut_function=(A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[59:71])
    defparam i2_3_lut_rep_337.init = 16'h8080;
    LUT4 i1_2_lut_rep_307_4_lut (.A(num[3]), .B(char[124]), .C(n29653), 
         .D(num[4]), .Z(n29583)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[59:71])
    defparam i1_2_lut_rep_307_4_lut.init = 16'h0080;
    LUT4 i22187_4_lut (.A(state[0]), .B(num_delay[2]), .C(n24_adj_1749), 
         .D(n19), .Z(num_delay_15__N_1194[2])) /* synthesis lut_function=(A (B+!(D))+!A !(B (C)+!B (C+(D)))) */ ;
    defparam i22187_4_lut.init = 16'h8caf;
    LUT4 i41_4_lut_adj_166 (.A(num_delay[2]), .B(n20968), .C(state[2]), 
         .D(n27524), .Z(n24_adj_1749)) /* synthesis lut_function=(!(A (B+!(C (D)))+!A (B (C)+!B !((D)+!C)))) */ ;
    defparam i41_4_lut_adj_166.init = 16'h3505;
    LUT4 i1_4_lut_adj_167 (.A(cnt_init[0]), .B(num_delay[2]), .C(n15_adj_1750), 
         .D(n29647), .Z(n27524)) /* synthesis lut_function=(!(A (B (D))+!A (B (C+(D))+!B (C)))) */ ;
    defparam i1_4_lut_adj_167.init = 16'h23af;
    LUT4 i1_4_lut_adj_168 (.A(num_delay[2]), .B(n29701), .C(n29646), .D(oled_dcn_N_1613), 
         .Z(n15_adj_1750)) /* synthesis lut_function=(A (B+(C))+!A !((D)+!C)) */ ;
    defparam i1_4_lut_adj_168.init = 16'ha8f8;
    LUT4 i14736_2_lut (.A(n479[14]), .B(oled_dcn_N_1613), .Z(n505[14])) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam i14736_2_lut.init = 16'h2222;
    LUT4 i2_2_lut_4_lut (.A(num[3]), .B(char[124]), .C(n29653), .D(n2132), 
         .Z(n27885)) /* synthesis lut_function=(A (B (C+(D))+!B (D))+!A (D)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[59:71])
    defparam i2_2_lut_4_lut.init = 16'hff80;
    LUT4 i14737_2_lut (.A(n479[13]), .B(oled_dcn_N_1613), .Z(n505[13])) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam i14737_2_lut.init = 16'h2222;
    LUT4 i1_4_lut_adj_169 (.A(state[0]), .B(num_delay[1]), .C(n16_adj_1751), 
         .D(n19), .Z(num_delay_15__N_1194[1])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_169.init = 16'hdc50;
    LUT4 i21958_3_lut (.A(min_h[3]), .B(min_l[3]), .C(\cnt_main[0] ), 
         .Z(n28109)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i21958_3_lut.init = 16'hcaca;
    LUT4 i14738_2_lut (.A(n479[12]), .B(oled_dcn_N_1613), .Z(n505[12])) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam i14738_2_lut.init = 16'h2222;
    LUT4 i2_3_lut_rep_339 (.A(num[3]), .B(n14962), .C(num[4]), .Z(n29615)) /* synthesis lut_function=(A+((C)+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[59:71])
    defparam i2_3_lut_rep_339.init = 16'hfbfb;
    LUT4 i33_4_lut_adj_170 (.A(num_delay[1]), .B(num_delay_15__N_1505[1]), 
         .C(state[2]), .D(n20968), .Z(n16_adj_1751)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_170.init = 16'h0aca;
    LUT4 i1_4_lut_adj_171 (.A(cnt_init[0]), .B(num_delay[9]), .C(n29580), 
         .D(n29647), .Z(num_delay_15__N_1505[9])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D)))) */ ;
    defparam i1_4_lut_adj_171.init = 16'hcc40;
    LUT4 i1_4_lut_adj_172 (.A(cnt_init[0]), .B(num_delay[1]), .C(n29580), 
         .D(n29647), .Z(num_delay_15__N_1505[1])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D)))) */ ;
    defparam i1_4_lut_adj_172.init = 16'hcc40;
    LUT4 i14623_2_lut_rep_308_4_lut (.A(num[3]), .B(n14962), .C(num[4]), 
         .D(char[0]), .Z(n29584)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[59:71])
    defparam i14623_2_lut_rep_308_4_lut.init = 16'h0400;
    LUT4 i1_4_lut_adj_173 (.A(n24_adj_1752), .B(state_back[5]), .C(n29625), 
         .D(n27_adj_1729), .Z(state_back_5__N_1248[5])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_173.init = 16'hce0a;
    PFUMX i21969 (.BLUT(n8), .ALUT(n9), .C0(cnt_main[1]), .Z(n28120));
    LUT4 i14739_2_lut (.A(n479[11]), .B(oled_dcn_N_1613), .Z(n505[11])) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam i14739_2_lut.init = 16'h2222;
    LUT4 i14581_2_lut_rep_306_4_lut (.A(num[3]), .B(n14962), .C(num[4]), 
         .D(char[6]), .Z(n29582)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[59:71])
    defparam i14581_2_lut_rep_306_4_lut.init = 16'h0400;
    LUT4 i14655_2_lut (.A(n2131), .B(num[4]), .Z(n846)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[59:71])
    defparam i14655_2_lut.init = 16'h2222;
    LUT4 i22243_3_lut (.A(num[2]), .B(num[1]), .C(num[0]), .Z(n14962)) /* synthesis lut_function=(!(A+(B+(C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[59:71])
    defparam i22243_3_lut.init = 16'h0101;
    LUT4 n29281_bdd_3_lut (.A(n1393), .B(n1771), .C(cnt_scan[0]), .Z(n29449)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n29281_bdd_3_lut.init = 16'hcaca;
    LUT4 i14740_2_lut (.A(n479[10]), .B(oled_dcn_N_1613), .Z(n505[10])) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam i14740_2_lut.init = 16'h2222;
    LUT4 i1_4_lut_adj_174 (.A(n24_adj_1753), .B(state_back[4]), .C(n29625), 
         .D(n27_adj_1729), .Z(state_back_5__N_1248[4])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_174.init = 16'hce0a;
    LUT4 i21957_3_lut (.A(\hour_h[3] ), .B(\hour_l[3] ), .C(\cnt_main[0] ), 
         .Z(n28108)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i21957_3_lut.init = 16'hcaca;
    LUT4 i1_3_lut_adj_175 (.A(cnt_init[0]), .B(num_delay[14]), .C(n29580), 
         .Z(n16_adj_1754)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
    defparam i1_3_lut_adj_175.init = 16'h4040;
    LUT4 char_5__bdd_4_lut (.A(char[5]), .B(num[1]), .C(char[13]), .D(num[0]), 
         .Z(n29466)) /* synthesis lut_function=(A (B (C)+!B (C+!(D)))+!A (B (C)+!B (C (D)))) */ ;
    defparam char_5__bdd_4_lut.init = 16'hf0e2;
    LUT4 i1_4_lut_adj_176 (.A(state[0]), .B(num_delay[8]), .C(n16_adj_1755), 
         .D(n19), .Z(num_delay_15__N_1194[8])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_176.init = 16'hdc50;
    LUT4 i1_4_lut_adj_177 (.A(n24_adj_1756), .B(state_back[3]), .C(n29625), 
         .D(n27_adj_1729), .Z(state_back_5__N_1248[3])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_177.init = 16'hce0a;
    LUT4 i33_4_lut_adj_178 (.A(num_delay[8]), .B(num_delay_15__N_1505[8]), 
         .C(state[2]), .D(n20968), .Z(n16_adj_1755)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_178.init = 16'h0aca;
    LUT4 i22163_2_lut_3_lut (.A(n21361), .B(n29547), .C(\cnt_main[0] ), 
         .Z(n20524)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;
    defparam i22163_2_lut_3_lut.init = 16'h0808;
    PFUMX i47 (.BLUT(n6_adj_1711), .ALUT(n12_adj_1730), .C0(state[3]), 
          .Z(n24_adj_1757));
    LUT4 i21956_3_lut (.A(temp_l[3]), .B(temp_p[3]), .C(\cnt_main[0] ), 
         .Z(n28107)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i21956_3_lut.init = 16'hcaca;
    FD1P3IX num_2277__i7 (.D(n37[7]), .SP(sys_clk_c_enable_108), .CD(n16671), 
            .CK(sys_clk_c), .Q(num[7])) /* synthesis syn_use_carry_chain=1 */ ;
    defparam num_2277__i7.GSR = "ENABLED";
    LUT4 n1676_bdd_2_lut_22752 (.A(n29452), .B(cnt_scan[1]), .Z(n29453)) /* synthesis lut_function=(A (B)) */ ;
    defparam n1676_bdd_2_lut_22752.init = 16'h8888;
    FD1P3IX num_2277__i6 (.D(n37[6]), .SP(sys_clk_c_enable_108), .CD(n16671), 
            .CK(sys_clk_c), .Q(num[6])) /* synthesis syn_use_carry_chain=1 */ ;
    defparam num_2277__i6.GSR = "ENABLED";
    LUT4 i14741_2_lut (.A(n479[9]), .B(oled_dcn_N_1613), .Z(n505[9])) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam i14741_2_lut.init = 16'h2222;
    PFUMX i47_adj_179 (.BLUT(n6_adj_1687), .ALUT(n12_adj_1736), .C0(state[3]), 
          .Z(n24_adj_1760));
    PFUMX i47_adj_180 (.BLUT(n6_adj_1712), .ALUT(n12_adj_1733), .C0(state[3]), 
          .Z(n24));
    PFUMX i47_adj_181 (.BLUT(n6_adj_1703), .ALUT(n12_adj_1731), .C0(state[3]), 
          .Z(n24_adj_1761));
    LUT4 i74_4_lut (.A(state[4]), .B(state[0]), .C(n29632), .D(n50_adj_1762), 
         .Z(n36_adj_1718)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;
    defparam i74_4_lut.init = 16'hcac0;
    PFUMX i47_adj_182 (.BLUT(n6_adj_1702), .ALUT(n12_adj_1737), .C0(state[3]), 
          .Z(n24_adj_1763));
    LUT4 i24_3_lut (.A(n12_adj_1764), .B(state[0]), .C(n29632), .Z(n27067)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i24_3_lut.init = 16'hcaca;
    PFUMX i47_adj_183 (.BLUT(n6_adj_1765), .ALUT(n12_adj_1738), .C0(state[3]), 
          .Z(n24_adj_1766));
    LUT4 n2146_bdd_3_lut (.A(n1390), .B(n1768), .C(cnt_scan[0]), .Z(n29277)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n2146_bdd_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_adj_184 (.A(n24_adj_1767), .B(state_back[2]), .C(n29625), 
         .D(n27_adj_1729), .Z(state_back_5__N_1248[2])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_184.init = 16'hce0a;
    LUT4 i21955_3_lut (.A(sign), .B(temp_h[3]), .C(\cnt_main[0] ), .Z(n28106)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam i21955_3_lut.init = 16'hcaca;
    PFUMX i47_adj_185 (.BLUT(n6_adj_1768), .ALUT(n12_adj_1732), .C0(state[3]), 
          .Z(n24_adj_1769));
    LUT4 i2_4_lut_adj_186 (.A(n29626), .B(state[4]), .C(oled_csn_N_1597), 
         .D(cnt_write[0]), .Z(n12_adj_1764)) /* synthesis lut_function=(!(A ((C+(D))+!B)+!A (((D)+!C)+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i2_4_lut_adj_186.init = 16'h0048;
    PFUMX i47_adj_187 (.BLUT(n6_adj_1770), .ALUT(n12_adj_1734), .C0(state[3]), 
          .Z(n24_adj_1771));
    LUT4 mux_1641_i1_4_lut (.A(n7507), .B(n27642), .C(n29596), .D(n4_adj_1772), 
         .Z(n5492[0])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam mux_1641_i1_4_lut.init = 16'hca0a;
    LUT4 n2146_bdd_3_lut_22627 (.A(n2146), .B(n2524), .C(cnt_scan[0]), 
         .Z(n29276)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n2146_bdd_3_lut_22627.init = 16'hcaca;
    LUT4 i1_2_lut_adj_188 (.A(cnt_init[0]), .B(cnt_init[1]), .Z(n4_adj_1772)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(108[7] 124[14])
    defparam i1_2_lut_adj_188.init = 16'h4444;
    LUT4 i1_4_lut_adj_189 (.A(n29591), .B(num_delay[8]), .C(n16_adj_1773), 
         .D(n29647), .Z(num_delay_15__N_1505[8])) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_189.init = 16'hfefa;
    FD1P3IX cnt_delay_i0_i3 (.D(n2606[3]), .SP(sys_clk_c_enable_131), .CD(n16582), 
            .CK(sys_clk_c), .Q(cnt_delay[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_delay_i0_i3.GSR = "ENABLED";
    LUT4 n2149_bdd_3_lut_22632 (.A(n2149), .B(n2527), .C(cnt_scan[0]), 
         .Z(n29281)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n2149_bdd_3_lut_22632.init = 16'hcaca;
    PFUMX i47_adj_190 (.BLUT(n6_adj_1682), .ALUT(n27589), .C0(state[3]), 
          .Z(n24_adj_1767));
    PFUMX i22471 (.BLUT(n28944), .ALUT(n28943), .C0(state[3]), .Z(n28945));
    LUT4 i1_4_lut_adj_191 (.A(n29591), .B(num_delay[14]), .C(n16_adj_1754), 
         .D(n29647), .Z(num_delay_15__N_1505[14])) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_191.init = 16'hfefa;
    LUT4 i14742_2_lut (.A(n479[8]), .B(oled_dcn_N_1613), .Z(n505[8])) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam i14742_2_lut.init = 16'h2222;
    LUT4 i1_3_lut_adj_192 (.A(cnt_init[0]), .B(num_delay[8]), .C(n29580), 
         .Z(n16_adj_1773)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
    defparam i1_3_lut_adj_192.init = 16'h4040;
    PFUMX i47_adj_193 (.BLUT(n6_adj_1720), .ALUT(n27591), .C0(state[3]), 
          .Z(n24_adj_1752));
    PFUMX i47_adj_194 (.BLUT(n6_adj_1722), .ALUT(n27590), .C0(state[3]), 
          .Z(n24_adj_1739));
    PFUMX i47_adj_195 (.BLUT(n6_adj_1677), .ALUT(n12_adj_1728), .C0(state[3]), 
          .Z(n24_adj_1756));
    CCU2D add_100_5 (.A0(cnt_delay[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_delay[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n24953), .COUT(n24954), .S0(n2606[3]), .S1(n2606[4]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(178[29:45])
    defparam add_100_5.INIT0 = 16'h5aaa;
    defparam add_100_5.INIT1 = 16'h5aaa;
    defparam add_100_5.INJECT1_0 = "NO";
    defparam add_100_5.INJECT1_1 = "NO";
    LUT4 shift_right_60_i2130_4_lut (.A(char[1]), .B(n1868), .C(num[3]), 
         .D(n14962), .Z(n2130)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[59:71])
    defparam shift_right_60_i2130_4_lut.init = 16'hcac0;
    PFUMX i47_adj_196 (.BLUT(n6_adj_1721), .ALUT(n27592), .C0(state[3]), 
          .Z(n24_adj_1753));
    PFUMX i21970 (.BLUT(n11), .ALUT(n12), .C0(cnt_main[1]), .Z(n28121));
    LUT4 i14270_4_lut (.A(n14962), .B(n1868), .C(num[3]), .D(char[3]), 
         .Z(n2132)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(52[12:15])
    defparam i14270_4_lut.init = 16'hcac0;
    LUT4 i3248_3_lut_rep_300_4_lut (.A(n29702), .B(n29701), .C(cnt_init[0]), 
         .D(oled_dcn_N_1613), .Z(n29576)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(122[8:12])
    defparam i3248_3_lut_rep_300_4_lut.init = 16'hfffe;
    LUT4 i2_4_lut_adj_197 (.A(n15556), .B(state[2]), .C(n35), .D(n31), 
         .Z(state_back_5__N_1248[1])) /* synthesis lut_function=(A+(B (C)+!B (C+(D)))) */ ;
    defparam i2_4_lut_adj_197.init = 16'hfbfa;
    LUT4 n2150_bdd_3_lut_22635 (.A(n2150), .B(n2528), .C(cnt_scan[0]), 
         .Z(n29284)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n2150_bdd_3_lut_22635.init = 16'hcaca;
    LUT4 i22098_1_lut_3_lut (.A(n29734), .B(n15389), .C(cnt_scan[0]), 
         .Z(n28194)) /* synthesis lut_function=(!(A (B (C))+!A (B+!(C)))) */ ;
    defparam i22098_1_lut_3_lut.init = 16'h3a3a;
    LUT4 n2151_bdd_3_lut_22638 (.A(n2151), .B(n2529), .C(cnt_scan[0]), 
         .Z(n29287)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n2151_bdd_3_lut_22638.init = 16'hcaca;
    LUT4 i2_3_lut_4_lut_adj_198 (.A(state[0]), .B(n29665), .C(state[3]), 
         .D(n29712), .Z(n11_adj_1717)) /* synthesis lut_function=(A+(((D)+!C)+!B)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(150[5:10])
    defparam i2_3_lut_4_lut_adj_198.init = 16'hffbf;
    LUT4 i22192_2_lut_3_lut_4_lut (.A(state[3]), .B(n29712), .C(n29665), 
         .D(state[0]), .Z(n28258)) /* synthesis lut_function=(!(A+(B+!((D)+!C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(75[5:9])
    defparam i22192_2_lut_3_lut_4_lut.init = 16'h1101;
    LUT4 i10541_2_lut_3_lut_4_lut (.A(state[3]), .B(n29712), .C(sys_clk_c_enable_122), 
         .D(n29637), .Z(n16615)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(75[5:9])
    defparam i10541_2_lut_3_lut_4_lut.init = 16'hf0e0;
    CCU2D add_100_3 (.A0(cnt_delay[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_delay[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n24952), .COUT(n24953), .S0(n2606[1]), .S1(n2606[2]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(178[29:45])
    defparam add_100_3.INIT0 = 16'h5aaa;
    defparam add_100_3.INIT1 = 16'h5aaa;
    defparam add_100_3.INJECT1_0 = "NO";
    defparam add_100_3.INJECT1_1 = "NO";
    CCU2D num_2277_add_4_9 (.A0(cnt_scan[3]), .B0(n15356), .C0(num[7]), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n25031), .S0(n37[7]));
    defparam num_2277_add_4_9.INIT0 = 16'he1e1;
    defparam num_2277_add_4_9.INIT1 = 16'h0000;
    defparam num_2277_add_4_9.INJECT1_0 = "NO";
    defparam num_2277_add_4_9.INJECT1_1 = "NO";
    LUT4 i1_4_lut_adj_199 (.A(state[0]), .B(n20968), .C(state[2]), .D(state_back_5__N_1583[1]), 
         .Z(n15556)) /* synthesis lut_function=(!(A (B+(C))+!A (B+!(C (D))))) */ ;
    defparam i1_4_lut_adj_199.init = 16'h1202;
    LUT4 i1_4_lut_adj_200 (.A(state_back[1]), .B(n29671), .C(n24_adj_1775), 
         .D(n29712), .Z(n35)) /* synthesis lut_function=(A (B+(C+(D)))) */ ;
    defparam i1_4_lut_adj_200.init = 16'haaa8;
    LUT4 i50_4_lut (.A(state_back[1]), .B(n2796), .C(state[3]), .D(n29625), 
         .Z(n31)) /* synthesis lut_function=(!((B (C (D))+!B (C))+!A)) */ ;
    defparam i50_4_lut.init = 16'h0a8a;
    LUT4 n29467_bdd_3_lut (.A(n29467), .B(char[53]), .C(num[3]), .Z(n2134)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n29467_bdd_3_lut.init = 16'hcaca;
    LUT4 i1_4_lut_adj_201 (.A(cnt_init[0]), .B(state_back[1]), .C(n29580), 
         .D(n29647), .Z(state_back_5__N_1583[1])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D)))) */ ;
    defparam i1_4_lut_adj_201.init = 16'hcc40;
    LUT4 i1_2_lut_adj_202 (.A(state[3]), .B(state[2]), .Z(n24_adj_1775)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_adj_202.init = 16'h8888;
    CCU2D num_2277_add_4_7 (.A0(cnt_scan[3]), .B0(n15356), .C0(num[5]), 
          .D0(GND_net), .A1(cnt_scan[3]), .B1(n15356), .C1(num[6]), 
          .D1(GND_net), .CIN(n25030), .COUT(n25031), .S0(n37[5]), .S1(n37[6]));
    defparam num_2277_add_4_7.INIT0 = 16'he1e1;
    defparam num_2277_add_4_7.INIT1 = 16'he1e1;
    defparam num_2277_add_4_7.INJECT1_0 = "NO";
    defparam num_2277_add_4_7.INJECT1_1 = "NO";
    LUT4 i1_4_lut_adj_203 (.A(n44_adj_1686), .B(n47), .C(n20949), .D(n29712), 
         .Z(n7769)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A ((D)+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i1_4_lut_adj_203.init = 16'h0ace;
    PFUMX i73 (.BLUT(n27497), .ALUT(n27_adj_1673), .C0(state[3]), .Z(n47_adj_1748));
    LUT4 i1_4_lut_adj_204 (.A(cnt_scan[4]), .B(n27626), .C(cnt_scan[2]), 
         .D(cnt_scan[3]), .Z(n2796)) /* synthesis lut_function=(A+(B (C+!(D))+!B (C (D)))) */ ;
    defparam i1_4_lut_adj_204.init = 16'hfaee;
    LUT4 i2_3_lut_4_lut_adj_205 (.A(state[3]), .B(n29712), .C(state[0]), 
         .D(n29665), .Z(n16634)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(75[5:9])
    defparam i2_3_lut_4_lut_adj_205.init = 16'h1000;
    LUT4 i1_4_lut_adj_206 (.A(state[0]), .B(num_delay[14]), .C(n16_adj_1776), 
         .D(n19), .Z(num_delay_15__N_1194[14])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_206.init = 16'hdc50;
    PFUMX i39 (.BLUT(n5), .ALUT(n9_adj_1724), .C0(state[2]), .Z(n20_adj_1699));
    LUT4 i1_4_lut_adj_207 (.A(n24_adj_1760), .B(char_reg_c[4]), .C(n29625), 
         .D(n27_adj_1729), .Z(char_reg_7__N_1166[4])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_207.init = 16'hce0a;
    CCU2D add_100_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_delay[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .COUT(n24952), .S1(n2606[0]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(178[29:45])
    defparam add_100_1.INIT0 = 16'hF000;
    defparam add_100_1.INIT1 = 16'h5555;
    defparam add_100_1.INJECT1_0 = "NO";
    defparam add_100_1.INJECT1_1 = "NO";
    LUT4 i2_3_lut_4_lut_adj_208 (.A(\cnt_main[0] ), .B(n29667), .C(state[1]), 
         .D(n29683), .Z(n27611)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam i2_3_lut_4_lut_adj_208.init = 16'h1000;
    LUT4 i1_2_lut_rep_292_3_lut_4_lut (.A(\cnt_main[0] ), .B(n29667), .C(cnt_main[3]), 
         .D(sign), .Z(n29568)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam i1_2_lut_rep_292_3_lut_4_lut.init = 16'hffef;
    LUT4 i1_4_lut_adj_209 (.A(state[0]), .B(num_delay[7]), .C(n16_adj_1777), 
         .D(n19), .Z(num_delay_15__N_1194[7])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_209.init = 16'hdc50;
    LUT4 i14743_2_lut (.A(n479[7]), .B(oled_dcn_N_1613), .Z(n505[7])) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam i14743_2_lut.init = 16'h2222;
    FD1P3IX cnt_delay_i0_i4 (.D(n2606[4]), .SP(sys_clk_c_enable_131), .CD(n16582), 
            .CK(sys_clk_c), .Q(cnt_delay[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_delay_i0_i4.GSR = "ENABLED";
    LUT4 i1_4_lut_adj_210 (.A(n24_adj_1771), .B(\char_reg[3] ), .C(n29625), 
         .D(n27_adj_1729), .Z(char_reg_7__N_1166[3])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_210.init = 16'hce0a;
    CCU2D num_2277_add_4_5 (.A0(cnt_scan[3]), .B0(n15356), .C0(num[3]), 
          .D0(GND_net), .A1(cnt_scan[3]), .B1(n15356), .C1(num[4]), 
          .D1(GND_net), .CIN(n25029), .COUT(n25030), .S0(n37[3]), .S1(n37[4]));
    defparam num_2277_add_4_5.INIT0 = 16'he1e1;
    defparam num_2277_add_4_5.INIT1 = 16'he1e1;
    defparam num_2277_add_4_5.INJECT1_0 = "NO";
    defparam num_2277_add_4_5.INJECT1_1 = "NO";
    LUT4 i33_4_lut_adj_211 (.A(num_delay[7]), .B(num_delay_15__N_1505[7]), 
         .C(state[2]), .D(n20968), .Z(n16_adj_1777)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_211.init = 16'h0aca;
    FD1P3IX cnt_delay_i0_i5 (.D(n2606[5]), .SP(sys_clk_c_enable_131), .CD(n16582), 
            .CK(sys_clk_c), .Q(cnt_delay[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_delay_i0_i5.GSR = "ENABLED";
    LUT4 i33_4_lut_adj_212 (.A(num_delay[14]), .B(num_delay_15__N_1505[14]), 
         .C(state[2]), .D(n20968), .Z(n16_adj_1776)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_212.init = 16'h0aca;
    FD1P3AX num_2277__i0 (.D(n1[0]), .SP(sys_clk_c_enable_112), .CK(sys_clk_c), 
            .Q(num[0])) /* synthesis syn_use_carry_chain=1 */ ;
    defparam num_2277__i0.GSR = "ENABLED";
    LUT4 i1_4_lut_adj_213 (.A(n29591), .B(num_delay[7]), .C(n16_adj_1778), 
         .D(n29647), .Z(num_delay_15__N_1505[7])) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_213.init = 16'hfefa;
    LUT4 i1_3_lut_adj_214 (.A(cnt_init[0]), .B(num_delay[7]), .C(n29580), 
         .Z(n16_adj_1778)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
    defparam i1_3_lut_adj_214.init = 16'h4040;
    CCU2D num_2277_add_4_3 (.A0(cnt_scan[3]), .B0(n15356), .C0(num[1]), 
          .D0(GND_net), .A1(cnt_scan[3]), .B1(n15356), .C1(num[2]), 
          .D1(GND_net), .CIN(n25028), .COUT(n25029), .S0(n37[1]), .S1(n37[2]));
    defparam num_2277_add_4_3.INIT0 = 16'he1e1;
    defparam num_2277_add_4_3.INIT1 = 16'he1e1;
    defparam num_2277_add_4_3.INJECT1_0 = "NO";
    defparam num_2277_add_4_3.INJECT1_1 = "NO";
    LUT4 mux_19_Mux_5_i15_3_lut_4_lut (.A(\cnt_main[0] ), .B(n29667), .C(cnt_main[3]), 
         .D(n29630), .Z(n15_adj_1685)) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C+(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam mux_19_Mux_5_i15_3_lut_4_lut.init = 16'h1f10;
    LUT4 i14411_2_lut_rep_298_3_lut_4_lut (.A(\cnt_main[0] ), .B(n29667), 
         .C(cnt_main[4]), .D(cnt_main[3]), .Z(n29574)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam i14411_2_lut_rep_298_3_lut_4_lut.init = 16'hf0e0;
    FD1P3IX cnt_delay_i0_i6 (.D(n2606[6]), .SP(sys_clk_c_enable_131), .CD(n16582), 
            .CK(sys_clk_c), .Q(cnt_delay[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_delay_i0_i6.GSR = "ENABLED";
    CCU2D num_2277_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_scan[3]), .B1(n15356), .C1(num[0]), 
          .D1(GND_net), .COUT(n25028), .S1(n37[0]));
    defparam num_2277_add_4_1.INIT0 = 16'hF000;
    defparam num_2277_add_4_1.INIT1 = 16'he1e1;
    defparam num_2277_add_4_1.INJECT1_0 = "NO";
    defparam num_2277_add_4_1.INJECT1_1 = "NO";
    LUT4 i14744_2_lut (.A(n479[6]), .B(oled_dcn_N_1613), .Z(n505[6])) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam i14744_2_lut.init = 16'h2222;
    CCU2D add_26_17 (.A0(cnt_c[15]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n24951), 
          .S0(n479[15]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam add_26_17.INIT0 = 16'h5aaa;
    defparam add_26_17.INIT1 = 16'h0000;
    defparam add_26_17.INJECT1_0 = "NO";
    defparam add_26_17.INJECT1_1 = "NO";
    LUT4 i10530_3_lut (.A(sys_clk_c_enable_131), .B(n11_adj_1707), .C(n2604), 
         .Z(n16582)) /* synthesis lut_function=(A (B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam i10530_3_lut.init = 16'ha8a8;
    LUT4 i14745_2_lut (.A(n479[5]), .B(oled_dcn_N_1613), .Z(n505[5])) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam i14745_2_lut.init = 16'h2222;
    LUT4 n11_bdd_4_lut_4_lut (.A(n29665), .B(n29621), .C(n29622), .D(n11_adj_1707), 
         .Z(sys_clk_c_enable_131)) /* synthesis lut_function=(!(A (B (C (D))+!B ((D)+!C))+!A (B (D)+!B ((D)+!C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam n11_bdd_4_lut_4_lut.init = 16'h08fc;
    LUT4 i14746_2_lut (.A(n479[4]), .B(oled_dcn_N_1613), .Z(n505[4])) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam i14746_2_lut.init = 16'h2222;
    LUT4 i15325_4_lut (.A(n29546), .B(n29547), .C(\cnt_main[0] ), .D(cnt_main[2]), 
         .Z(sys_clk_c_enable_38)) /* synthesis lut_function=(A (B)+!A (B (C+(D)))) */ ;
    defparam i15325_4_lut.init = 16'hccc8;
    PFUMX i22012 (.BLUT(n28159), .ALUT(n28160), .C0(cnt_write[2]), .Z(n28163));
    LUT4 i1_4_lut_adj_215 (.A(cnt_main[2]), .B(n29555), .C(n29664), .D(cnt_main[3]), 
         .Z(n21361)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i1_4_lut_adj_215.init = 16'hfffe;
    LUT4 n8_bdd_4_lut_4_lut (.A(n29665), .B(n29622), .C(n11_adj_1717), 
         .D(n29621), .Z(sys_clk_c_enable_106)) /* synthesis lut_function=(!(A (B (C)+!B !(D))+!A (B (C)+!B (C+!(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam n8_bdd_4_lut_4_lut.init = 16'h2f0c;
    LUT4 i14574_4_lut (.A(cnt_main[3]), .B(n29567), .C(cnt_main[4]), .D(n4_adj_1779), 
         .Z(n4593[0])) /* synthesis lut_function=(A (B (C))+!A (B (C+(D)))) */ ;
    defparam i14574_4_lut.init = 16'hc4c0;
    LUT4 i1_3_lut_adj_216 (.A(\cnt_main[0] ), .B(cnt_main[1]), .C(cnt_main[2]), 
         .Z(n4_adj_1779)) /* synthesis lut_function=(!(A+(B (C)+!B !(C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(78[7] 105[14])
    defparam i1_3_lut_adj_216.init = 16'h1414;
    PFUMX i22013 (.BLUT(n28161), .ALUT(n28162), .C0(cnt_write[2]), .Z(n28164));
    LUT4 i1_4_lut_adj_217 (.A(state[0]), .B(num_delay[6]), .C(n16_adj_1780), 
         .D(n19), .Z(num_delay_15__N_1194[6])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_217.init = 16'hdc50;
    LUT4 n1017_bdd_3_lut_22908 (.A(n1017), .B(cnt_scan[2]), .C(cnt_scan[1]), 
         .Z(n29333)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam n1017_bdd_3_lut_22908.init = 16'h8080;
    LUT4 n1017_bdd_4_lut (.A(y_p[0]), .B(cnt_scan[2]), .C(x_ph[0]), .D(cnt_scan[1]), 
         .Z(n29334)) /* synthesis lut_function=(!(A (B+!(C+!(D)))+!A (B+!(C (D))))) */ ;
    defparam n1017_bdd_4_lut.init = 16'h3022;
    LUT4 n11_bdd_4_lut_4_lut_adj_218 (.A(n29665), .B(n29621), .C(n29622), 
         .D(n11_adj_1680), .Z(sys_clk_c_enable_121)) /* synthesis lut_function=(!(A (B (C (D))+!B ((D)+!C))+!A (B (D)+!B ((D)+!C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam n11_bdd_4_lut_4_lut_adj_218.init = 16'h08fc;
    PFUMX i67 (.BLUT(n18), .ALUT(n24_adj_1746), .C0(state[3]), .Z(n41_adj_1696));
    LUT4 i14747_2_lut (.A(n479[3]), .B(oled_dcn_N_1613), .Z(n505[3])) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam i14747_2_lut.init = 16'h2222;
    LUT4 i33_4_lut_adj_219 (.A(num_delay[6]), .B(num_delay_15__N_1505[6]), 
         .C(state[2]), .D(n20968), .Z(n16_adj_1780)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_219.init = 16'h0aca;
    LUT4 i1_4_lut_adj_220 (.A(cnt_init[0]), .B(num_delay[6]), .C(n29580), 
         .D(n29647), .Z(num_delay_15__N_1505[6])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D)))) */ ;
    defparam i1_4_lut_adj_220.init = 16'hcc40;
    FD1P3IX cnt_delay_i0_i7 (.D(n2606[7]), .SP(sys_clk_c_enable_131), .CD(n16582), 
            .CK(sys_clk_c), .Q(cnt_delay[7])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_delay_i0_i7.GSR = "ENABLED";
    LUT4 i14626_2_lut (.A(state[4]), .B(state_back[0]), .Z(n41)) /* synthesis lut_function=(!(A+(B))) */ ;
    defparam i14626_2_lut.init = 16'h1111;
    LUT4 i14748_2_lut (.A(n479[2]), .B(oled_dcn_N_1613), .Z(n505[2])) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam i14748_2_lut.init = 16'h2222;
    LUT4 n1016_bdd_3_lut_22927 (.A(n1016), .B(cnt_scan[2]), .C(cnt_scan[1]), 
         .Z(n29348)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam n1016_bdd_3_lut_22927.init = 16'h8080;
    LUT4 i1_4_lut_adj_221 (.A(state[4]), .B(state[0]), .C(n29626), .D(n29570), 
         .Z(n34)) /* synthesis lut_function=(!((B (C+!(D))+!B (C (D)))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(66[4] 181[11])
    defparam i1_4_lut_adj_221.init = 16'h0a22;
    PFUMX i91 (.BLUT(n45_adj_1698), .ALUT(n57_adj_1727), .C0(n28048), 
          .Z(n63));
    LUT4 i14657_2_lut_rep_286 (.A(n2134), .B(num[4]), .Z(n29562)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[59:71])
    defparam i14657_2_lut_rep_286.init = 16'h2222;
    LUT4 i1_2_lut_4_lut_adj_222 (.A(n28720), .B(n2052), .C(n29560), .D(state[2]), 
         .Z(n6_adj_1770)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A !((C+!(D))+!B)) */ ;
    defparam i1_2_lut_4_lut_adj_222.init = 16'hac00;
    PFUMX i8517 (.BLUT(n28193), .ALUT(n28194), .C0(n29562), .Z(n25598));
    LUT4 i1_2_lut_3_lut_4_lut_adj_223 (.A(cnt_init[2]), .B(n29702), .C(state[4]), 
         .D(cnt_init[0]), .Z(n6_adj_1723)) /* synthesis lut_function=(!(A+(B+((D)+!C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(112[8:12])
    defparam i1_2_lut_3_lut_4_lut_adj_223.init = 16'h0010;
    LUT4 i2_2_lut_3_lut_4_lut (.A(n2134), .B(num[4]), .C(n29711), .D(n29582), 
         .Z(n6_adj_1688)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[59:71])
    defparam i2_2_lut_3_lut_4_lut.init = 16'h2000;
    LUT4 i1_2_lut_4_lut_adj_224 (.A(n22_adj_1), .B(n2053), .C(n28077), 
         .D(state[2]), .Z(n6_adj_1768)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A !((C+!(D))+!B)) */ ;
    defparam i1_2_lut_4_lut_adj_224.init = 16'hac00;
    LUT4 i73_2_lut_3_lut_4_lut (.A(cnt_write[1]), .B(n29673), .C(oled_csn_N_1597), 
         .D(cnt_write[0]), .Z(n50_adj_1762)) /* synthesis lut_function=(!(A (C)+!A (B (C)+!B (C (D)+!C !(D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(153[7] 173[14])
    defparam i73_2_lut_3_lut_4_lut.init = 16'h0f1e;
    LUT4 i1_4_lut_adj_225 (.A(state[0]), .B(num_delay[5]), .C(n16_adj_1782), 
         .D(n19), .Z(num_delay_15__N_1194[5])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_225.init = 16'hdc50;
    FD1P3IX cnt_delay_i0_i8 (.D(n2606[8]), .SP(sys_clk_c_enable_131), .CD(n16582), 
            .CK(sys_clk_c), .Q(cnt_delay[8])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_delay_i0_i8.GSR = "ENABLED";
    LUT4 n29424_bdd_2_lut (.A(n29424), .B(cnt_scan[4]), .Z(n29425)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam n29424_bdd_2_lut.init = 16'h2222;
    LUT4 i15157_2_lut_rep_294_3_lut_4_lut (.A(cnt_write[1]), .B(n29673), 
         .C(oled_csn_N_1597), .D(cnt_write[0]), .Z(n29570)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(153[7] 173[14])
    defparam i15157_2_lut_rep_294_3_lut_4_lut.init = 16'hf0e0;
    LUT4 i33_4_lut_adj_226 (.A(num_delay[5]), .B(num_delay_15__N_1505[5]), 
         .C(state[2]), .D(n20968), .Z(n16_adj_1782)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_226.init = 16'h0aca;
    LUT4 n1016_bdd_4_lut (.A(y_p[1]), .B(cnt_scan[2]), .C(x_ph[1]), .D(cnt_scan[1]), 
         .Z(n29349)) /* synthesis lut_function=(!(A (B+!(C+!(D)))+!A (B+!(C (D))))) */ ;
    defparam n1016_bdd_4_lut.init = 16'h3022;
    LUT4 i1_4_lut_adj_227 (.A(n24_adj_1769), .B(\char_reg[2] ), .C(n29625), 
         .D(n27_adj_1729), .Z(char_reg_7__N_1166[2])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_227.init = 16'hce0a;
    PFUMX i58 (.BLUT(n6), .ALUT(n12_adj_1726), .C0(state[2]), .Z(n32));
    LUT4 i1_4_lut_adj_228 (.A(n29591), .B(num_delay[5]), .C(n16_adj_1783), 
         .D(n29647), .Z(num_delay_15__N_1505[5])) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_228.init = 16'hfefa;
    LUT4 i1_2_lut_4_lut_adj_229 (.A(n28732), .B(n2049), .C(n28063), .D(state[2]), 
         .Z(n6_adj_1765)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A !((C+!(D))+!B)) */ ;
    defparam i1_2_lut_4_lut_adj_229.init = 16'hac00;
    LUT4 n843_bdd_2_lut_22728_3_lut (.A(n2134), .B(num[4]), .C(n125), 
         .Z(n29419)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[59:71])
    defparam n843_bdd_2_lut_22728_3_lut.init = 16'h2020;
    FD1P3AX y_p_i0_i1 (.D(n4593[1]), .SP(sys_clk_c_enable_116), .CK(sys_clk_c), 
            .Q(y_p[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam y_p_i0_i1.GSR = "ENABLED";
    LUT4 i1_3_lut_adj_230 (.A(cnt_init[0]), .B(num_delay[5]), .C(n29580), 
         .Z(n16_adj_1783)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
    defparam i1_3_lut_adj_230.init = 16'h4040;
    FD1P3IX cnt_write_i0_i4 (.D(n2582[4]), .SP(sys_clk_c_enable_121), .CD(n16617), 
            .CK(sys_clk_c), .Q(oled_csn_N_1597)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_write_i0_i4.GSR = "ENABLED";
    LUT4 i1_4_lut_adj_231 (.A(n24_adj_1757), .B(char_reg[7]), .C(n29625), 
         .D(n27_adj_1729), .Z(char_reg_7__N_1166[7])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_231.init = 16'hce0a;
    FD1P3IX cnt_write_i0_i3 (.D(n2582[3]), .SP(sys_clk_c_enable_121), .CD(n16617), 
            .CK(sys_clk_c), .Q(cnt_write[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_write_i0_i3.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i9 (.D(n2606[9]), .SP(sys_clk_c_enable_131), .CD(n16582), 
            .CK(sys_clk_c), .Q(cnt_delay[9])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_delay_i0_i9.GSR = "ENABLED";
    FD1P3IX cnt_write_i0_i2 (.D(n2582[2]), .SP(sys_clk_c_enable_121), .CD(n16617), 
            .CK(sys_clk_c), .Q(cnt_write[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_write_i0_i2.GSR = "ENABLED";
    FD1P3IX cnt_write_i0_i1 (.D(n2582[1]), .SP(sys_clk_c_enable_121), .CD(n16617), 
            .CK(sys_clk_c), .Q(cnt_write[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_write_i0_i1.GSR = "ENABLED";
    FD1P3IX cnt_i0_i0 (.D(n505[0]), .SP(sys_clk_c_enable_122), .CD(n16615), 
            .CK(sys_clk_c), .Q(\cnt[0] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_i0_i0.GSR = "ENABLED";
    LUT4 i1_4_lut_adj_232 (.A(n24_adj_1766), .B(char_reg[6]), .C(n29625), 
         .D(n27_adj_1729), .Z(char_reg_7__N_1166[6])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_232.init = 16'hce0a;
    LUT4 i14656_2_lut_rep_287 (.A(n2132), .B(num[4]), .Z(n29563)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(141[59:71])
    defparam i14656_2_lut_rep_287.init = 16'h2222;
    PFUMX i91_adj_233 (.BLUT(n57_adj_1714), .ALUT(n61), .C0(cnt_scan[3]), 
          .Z(n63_adj_1666));
    CCU2D add_26_15 (.A0(cnt_c[13]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_c[14]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n24950), .COUT(n24951), .S0(n479[13]), .S1(n479[14]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam add_26_15.INIT0 = 16'h5aaa;
    defparam add_26_15.INIT1 = 16'h5aaa;
    defparam add_26_15.INJECT1_0 = "NO";
    defparam add_26_15.INJECT1_1 = "NO";
    LUT4 i2_4_lut_rep_356 (.A(state[0]), .B(n29712), .C(state[1]), .D(n29682), 
         .Z(n29632)) /* synthesis lut_function=(!(A (B+(C+(D)))+!A (B+((D)+!C)))) */ ;
    defparam i2_4_lut_rep_356.init = 16'h0012;
    LUT4 i2072_2_lut_4_lut (.A(state[0]), .B(n29712), .C(state[1]), .D(n29682), 
         .Z(n7507)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;
    defparam i2072_2_lut_4_lut.init = 16'h0002;
    LUT4 i1_4_lut_adj_234 (.A(n24_adj_1763), .B(char_reg_c[5]), .C(n29625), 
         .D(n27_adj_1729), .Z(char_reg_7__N_1166[5])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_234.init = 16'hce0a;
    LUT4 n29284_bdd_3_lut (.A(n1394), .B(n1772), .C(cnt_scan[0]), .Z(n29381)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n29284_bdd_3_lut.init = 16'hcaca;
    PFUMX i22019 (.BLUT(n28166), .ALUT(n28167), .C0(cnt_main[1]), .Z(n28170));
    PFUMX i30 (.BLUT(n27611), .ALUT(n17), .C0(state[2]), .Z(n13_adj_1700));
    LUT4 n29348_bdd_3_lut_23258 (.A(n29348), .B(n29349), .C(cnt_scan[0]), 
         .Z(n29384)) /* synthesis lut_function=(A (B+(C))+!A !((C)+!B)) */ ;
    defparam n29348_bdd_3_lut_23258.init = 16'hacac;
    PFUMX i21974 (.BLUT(n28123), .ALUT(n28124), .C0(cnt_scan[1]), .Z(n28125));
    FD1P3AX x_ph_i0_i1 (.D(n4519[1]), .SP(sys_clk_c_enable_123), .CK(sys_clk_c), 
            .Q(x_ph[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam x_ph_i0_i1.GSR = "ENABLED";
    FD1P3AX x_ph_i0_i2 (.D(n27451), .SP(sys_clk_c_enable_125), .CK(sys_clk_c), 
            .Q(x_ph[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam x_ph_i0_i2.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i10 (.D(n2606[10]), .SP(sys_clk_c_enable_131), 
            .CD(n16582), .CK(sys_clk_c), .Q(cnt_delay[10])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_delay_i0_i10.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i11 (.D(n2606[11]), .SP(sys_clk_c_enable_131), 
            .CD(n16582), .CK(sys_clk_c), .Q(cnt_delay[11])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_delay_i0_i11.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i12 (.D(n2606[12]), .SP(sys_clk_c_enable_131), 
            .CD(n16582), .CK(sys_clk_c), .Q(cnt_delay[12])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_delay_i0_i12.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i13 (.D(n2606[13]), .SP(sys_clk_c_enable_131), 
            .CD(n16582), .CK(sys_clk_c), .Q(cnt_delay[13])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_delay_i0_i13.GSR = "ENABLED";
    FD1P3IX cnt_delay_i0_i14 (.D(n2606[14]), .SP(sys_clk_c_enable_131), 
            .CD(n16582), .CK(sys_clk_c), .Q(cnt_delay[14])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_delay_i0_i14.GSR = "ENABLED";
    LUT4 i1_4_lut_adj_235 (.A(n24_adj_1761), .B(\char_reg[1] ), .C(n29625), 
         .D(n27_adj_1729), .Z(char_reg_7__N_1166[1])) /* synthesis lut_function=(A (B ((D)+!C)+!B !(C))+!A (B (D))) */ ;
    defparam i1_4_lut_adj_235.init = 16'hce0a;
    FD1P3IX cnt_delay_i0_i15 (.D(n2606[15]), .SP(sys_clk_c_enable_131), 
            .CD(n16582), .CK(sys_clk_c), .Q(cnt_delay[15])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_delay_i0_i15.GSR = "ENABLED";
    FD1P3IX cnt_main_i0_i1 (.D(n29685), .SP(sys_clk_c_enable_136), .CD(n22754), 
            .CK(sys_clk_c), .Q(cnt_main[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_main_i0_i1.GSR = "ENABLED";
    FD1P3IX cnt_main_i0_i2 (.D(n2[2]), .SP(sys_clk_c_enable_136), .CD(n22754), 
            .CK(sys_clk_c), .Q(cnt_main[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_main_i0_i2.GSR = "ENABLED";
    FD1P3AX char_i0_i2 (.D(n27668), .SP(sys_clk_c_enable_135), .CK(sys_clk_c), 
            .Q(char[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam char_i0_i2.GSR = "ENABLED";
    LUT4 n29385_bdd_2_lut (.A(n29385), .B(cnt_scan[4]), .Z(n29386)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam n29385_bdd_2_lut.init = 16'h2222;
    LUT4 n29287_bdd_3_lut (.A(n1395), .B(n1773), .C(cnt_scan[0]), .Z(n29387)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;
    defparam n29287_bdd_3_lut.init = 16'hcaca;
    LUT4 n29333_bdd_3_lut_23252 (.A(n29333), .B(n29334), .C(cnt_scan[0]), 
         .Z(n29390)) /* synthesis lut_function=(A (B+(C))+!A !((C)+!B)) */ ;
    defparam n29333_bdd_3_lut_23252.init = 16'hacac;
    PFUMX i22020 (.BLUT(n28168), .ALUT(n28169), .C0(cnt_main[1]), .Z(n28171));
    LUT4 i14782_4_lut (.A(cnt_main[3]), .B(n29567), .C(cnt_main[4]), .D(n29616), 
         .Z(n4805[3])) /* synthesis lut_function=(A (B (C+!(D)))+!A (B (C+(D)))) */ ;
    defparam i14782_4_lut.init = 16'hc4c8;
    LUT4 n29391_bdd_2_lut (.A(n29391), .B(cnt_scan[4]), .Z(n29392)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam n29391_bdd_2_lut.init = 16'h2222;
    FD1P3AX char_i0_i3 (.D(n27667), .SP(sys_clk_c_enable_135), .CK(sys_clk_c), 
            .Q(char[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam char_i0_i3.GSR = "ENABLED";
    LUT4 i1_4_lut_adj_236 (.A(state[0]), .B(num_delay[4]), .C(n16_adj_1784), 
         .D(n19), .Z(num_delay_15__N_1194[4])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_236.init = 16'hdc50;
    LUT4 n843_bdd_2_lut (.A(cnt_scan[0]), .B(n63_adj_1672), .Z(n29420)) /* synthesis lut_function=(A (B)) */ ;
    defparam n843_bdd_2_lut.init = 16'h8888;
    FD1P3IX cnt_main_i0_i4 (.D(n8312), .SP(sys_clk_c_enable_136), .CD(n22754), 
            .CK(sys_clk_c), .Q(cnt_main[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam cnt_main_i0_i4.GSR = "ENABLED";
    LUT4 i33_4_lut_adj_237 (.A(num_delay[4]), .B(num_delay_15__N_1505[4]), 
         .C(state[2]), .D(n20968), .Z(n16_adj_1784)) /* synthesis lut_function=(!(A (B (C (D))+!B (C))+!A (((D)+!C)+!B))) */ ;
    defparam i33_4_lut_adj_237.init = 16'h0aca;
    LUT4 i1_4_lut_adj_238 (.A(cnt_init[0]), .B(num_delay[4]), .C(n29580), 
         .D(n29647), .Z(num_delay_15__N_1505[4])) /* synthesis lut_function=(A (B (D))+!A (B (C+(D)))) */ ;
    defparam i1_4_lut_adj_238.init = 16'hcc40;
    CCU2D add_26_13 (.A0(cnt_c[11]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_c[12]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n24949), .COUT(n24950), .S0(n479[11]), .S1(n479[12]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam add_26_13.INIT0 = 16'h5aaa;
    defparam add_26_13.INIT1 = 16'h5aaa;
    defparam add_26_13.INJECT1_0 = "NO";
    defparam add_26_13.INJECT1_1 = "NO";
    CCU2D add_26_11 (.A0(cnt_c[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_c[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n24948), .COUT(n24949), .S0(n479[9]), .S1(n479[10]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam add_26_11.INIT0 = 16'h5aaa;
    defparam add_26_11.INIT1 = 16'h5aaa;
    defparam add_26_11.INJECT1_0 = "NO";
    defparam add_26_11.INJECT1_1 = "NO";
    PFUMX i22797 (.BLUT(n29738), .ALUT(n29739), .C0(cnt_main[4]), .Z(n29740));
    PFUMX i22795 (.BLUT(n29735), .ALUT(n29736), .C0(\cnt_main[0] ), .Z(n29737));
    PFUMX i22793 (.BLUT(n29732), .ALUT(n29733), .C0(n29583), .Z(n29734));
    FD1P3AX char_i0_i5 (.D(n6420[5]), .SP(sys_clk_c_enable_137), .CK(sys_clk_c), 
            .Q(char[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=11, LSE_RCOL=2, LSE_LLINE=479, LSE_RLINE=497 */ ;   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(65[12] 182[6])
    defparam char_i0_i5.GSR = "ENABLED";
    PFUMX i22789 (.BLUT(n29724), .ALUT(n29725), .C0(state[4]), .Z(n29726));
    CCU2D add_26_9 (.A0(cnt_c[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt_c[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n24947), 
          .COUT(n24948), .S0(n479[7]), .S1(n479[8]));   // f:/git/my/fpga/training_v2.0/code/oled/yinhe/oled12832.v(118[19:29])
    defparam add_26_9.INIT0 = 16'h5aaa;
    defparam add_26_9.INIT1 = 16'h5aaa;
    defparam add_26_9.INJECT1_0 = "NO";
    defparam add_26_9.INJECT1_1 = "NO";
    PFUMX i22775 (.BLUT(n27623), .ALUT(n29520), .C0(state[2]), .Z(n29521));
    
endmodule
//
// Verilog Description of module divide
//

module divide (GND_net, sys_clk_c, sys_clk_N_7, sys_rst_n_c, clock) /* synthesis syn_module_defined=1 */ ;
    input GND_net;
    input sys_clk_c;
    input sys_clk_N_7;
    input sys_rst_n_c;
    output clock;
    
    wire sys_clk_c /* synthesis SET_AS_NETWORK=sys_clk_c, is_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(12[19:26])
    wire sys_clk_N_7 /* synthesis is_inv_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(44[11:27])
    wire clock /* synthesis SET_AS_NETWORK=clock, is_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(419[6:11])
    
    wire n25005;
    wire [23:0]cnt_n;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(27[25:30])
    wire [23:0]n77;
    
    wire n25006, n25004, clk_p, clk_p_N_959, clk_n, sys_rst_n_N_484, 
        clk_n_N_962;
    wire [23:0]cnt_p;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(27[19:24])
    
    wire n29687, n11, n9, n8, n16621, n27441, n13, n11_adj_1638, 
        n27799, n27511, n10, n27568, n28014, n28327, n28012, n16622, 
        n28010, n26, n12;
    wire [23:0]n77_adj_1665;
    
    wire n25173, n25194, n6, n4, n21337, n25414, n12_adj_1662, 
        n25253, n27569, n5, n6_adj_1663, n21339, n27443, n25027, 
        n25026, n25025, n25024, n25023, n25022, n25021, n25020, 
        n25019, n25018, n25017, n25016, n25015, n25014, n25013, 
        n25012, n25011, n25010, n25009, n25008, n25007;
    
    CCU2D cnt_n_2275_add_4_5 (.A0(cnt_n[3]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_n[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n25005), .COUT(n25006), .S0(n77[3]), .S1(n77[4]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275_add_4_5.INIT0 = 16'hfaaa;
    defparam cnt_n_2275_add_4_5.INIT1 = 16'hfaaa;
    defparam cnt_n_2275_add_4_5.INJECT1_0 = "NO";
    defparam cnt_n_2275_add_4_5.INJECT1_1 = "NO";
    CCU2D cnt_n_2275_add_4_3 (.A0(cnt_n[1]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_n[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n25004), .COUT(n25005), .S0(n77[1]), .S1(n77[2]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275_add_4_3.INIT0 = 16'hfaaa;
    defparam cnt_n_2275_add_4_3.INIT1 = 16'hfaaa;
    defparam cnt_n_2275_add_4_3.INJECT1_0 = "NO";
    defparam cnt_n_2275_add_4_3.INJECT1_1 = "NO";
    FD1S3AX clk_p_30 (.D(clk_p_N_959), .CK(sys_clk_c), .Q(clk_p)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=8, LSE_RCOL=2, LSE_LLINE=420, LSE_RLINE=424 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(46[9] 49[14])
    defparam clk_p_30.GSR = "ENABLED";
    CCU2D cnt_n_2275_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_n[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .COUT(n25004), .S1(n77[0]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275_add_4_1.INIT0 = 16'hF000;
    defparam cnt_n_2275_add_4_1.INIT1 = 16'h0555;
    defparam cnt_n_2275_add_4_1.INJECT1_0 = "NO";
    defparam cnt_n_2275_add_4_1.INJECT1_1 = "NO";
    FD1S3IX clk_n_32 (.D(clk_n_N_962), .CK(sys_clk_N_7), .CD(sys_rst_n_N_484), 
            .Q(clk_n)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=8, LSE_RCOL=2, LSE_LLINE=420, LSE_RLINE=424 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(63[9] 71[6])
    defparam clk_n_32.GSR = "DISABLED";
    LUT4 i1_2_lut_rep_411 (.A(cnt_p[14]), .B(cnt_p[13]), .Z(n29687)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(27[19:24])
    defparam i1_2_lut_rep_411.init = 16'heeee;
    LUT4 i4_3_lut_4_lut (.A(cnt_p[14]), .B(cnt_p[13]), .C(cnt_p[10]), 
         .D(cnt_p[22]), .Z(n11)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(27[19:24])
    defparam i4_3_lut_4_lut.init = 16'hfffe;
    LUT4 i5_4_lut (.A(n9), .B(cnt_n[12]), .C(n8), .D(cnt_n[18]), .Z(n16621)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i5_4_lut.init = 16'h8000;
    LUT4 i3_4_lut (.A(n27441), .B(n13), .C(n11_adj_1638), .D(n27799), 
         .Z(n9)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;
    defparam i3_4_lut.init = 16'h0080;
    LUT4 i2_2_lut (.A(cnt_n[7]), .B(cnt_n[9]), .Z(n8)) /* synthesis lut_function=(A (B)) */ ;
    defparam i2_2_lut.init = 16'h8888;
    LUT4 i5_4_lut_adj_36 (.A(n27511), .B(cnt_n[0]), .C(cnt_n[19]), .D(cnt_n[13]), 
         .Z(n13)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ;
    defparam i5_4_lut_adj_36.init = 16'h0002;
    LUT4 i3_3_lut (.A(cnt_n[2]), .B(cnt_n[15]), .C(cnt_n[21]), .Z(n11_adj_1638)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;
    defparam i3_3_lut.init = 16'h2020;
    LUT4 i21667_2_lut (.A(cnt_n[8]), .B(cnt_n[14]), .Z(n27799)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i21667_2_lut.init = 16'heeee;
    LUT4 i5_4_lut_adj_37 (.A(cnt_n[22]), .B(n10), .C(n27568), .D(cnt_n[10]), 
         .Z(n27511)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam i5_4_lut_adj_37.init = 16'h0040;
    LUT4 i4_4_lut (.A(cnt_n[20]), .B(cnt_n[11]), .C(cnt_n[23]), .D(cnt_n[5]), 
         .Z(n10)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam i4_4_lut.init = 16'h8000;
    LUT4 i22262_3_lut (.A(n28014), .B(n28327), .C(n28012), .Z(n16622)) /* synthesis lut_function=(A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam i22262_3_lut.init = 16'h8080;
    LUT4 i21866_4_lut (.A(cnt_p[16]), .B(cnt_p[3]), .C(cnt_p[18]), .D(cnt_p[20]), 
         .Z(n28014)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i21866_4_lut.init = 16'h8000;
    LUT4 i22261_4_lut (.A(n28010), .B(cnt_p[23]), .C(n26), .D(cnt_p[1]), 
         .Z(n28327)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam i22261_4_lut.init = 16'h0800;
    LUT4 i21864_4_lut (.A(cnt_p[21]), .B(cnt_p[7]), .C(cnt_p[5]), .D(cnt_p[9]), 
         .Z(n28012)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i21864_4_lut.init = 16'h8000;
    LUT4 i21862_4_lut (.A(cnt_p[11]), .B(cnt_p[2]), .C(cnt_p[17]), .D(cnt_p[4]), 
         .Z(n28010)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i21862_4_lut.init = 16'h8000;
    LUT4 i9_4_lut (.A(cnt_p[6]), .B(n11), .C(cnt_p[12]), .D(n12), .Z(n26)) /* synthesis lut_function=((B+((D)+!C))+!A) */ ;
    defparam i9_4_lut.init = 16'hffdf;
    LUT4 i5_4_lut_adj_38 (.A(cnt_p[19]), .B(cnt_p[8]), .C(cnt_p[0]), .D(cnt_p[15]), 
         .Z(n12)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(27[19:24])
    defparam i5_4_lut_adj_38.init = 16'hfffe;
    FD1S3IX cnt_n_2275__i1 (.D(n77[1]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i1.GSR = "ENABLED";
    FD1S3IX cnt_n_2275__i2 (.D(n77[2]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i2.GSR = "ENABLED";
    FD1S3IX cnt_n_2275__i3 (.D(n77[3]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i3.GSR = "ENABLED";
    FD1S3IX cnt_n_2275__i4 (.D(n77[4]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i4.GSR = "ENABLED";
    FD1S3IX cnt_n_2275__i5 (.D(n77[5]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i5.GSR = "ENABLED";
    FD1S3IX cnt_n_2275__i6 (.D(n77[6]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i6.GSR = "ENABLED";
    FD1S3IX cnt_n_2275__i7 (.D(n77[7]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[7])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i7.GSR = "ENABLED";
    FD1S3IX cnt_n_2275__i8 (.D(n77[8]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[8])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i8.GSR = "ENABLED";
    FD1S3IX cnt_n_2275__i9 (.D(n77[9]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[9])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i9.GSR = "ENABLED";
    FD1S3IX cnt_n_2275__i10 (.D(n77[10]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[10])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i10.GSR = "ENABLED";
    FD1S3IX cnt_n_2275__i11 (.D(n77[11]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[11])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i11.GSR = "ENABLED";
    FD1S3IX cnt_n_2275__i12 (.D(n77[12]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[12])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i12.GSR = "ENABLED";
    FD1S3IX cnt_n_2275__i13 (.D(n77[13]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[13])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i13.GSR = "ENABLED";
    FD1S3IX cnt_n_2275__i14 (.D(n77[14]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[14])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i14.GSR = "ENABLED";
    FD1S3IX cnt_n_2275__i15 (.D(n77[15]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[15])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i15.GSR = "ENABLED";
    FD1S3IX cnt_n_2275__i16 (.D(n77[16]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[16])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i16.GSR = "ENABLED";
    FD1S3IX cnt_n_2275__i17 (.D(n77[17]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[17])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i17.GSR = "ENABLED";
    FD1S3IX cnt_n_2275__i18 (.D(n77[18]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[18])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i18.GSR = "ENABLED";
    FD1S3IX cnt_n_2275__i19 (.D(n77[19]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[19])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i19.GSR = "ENABLED";
    FD1S3IX cnt_n_2275__i20 (.D(n77[20]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[20])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i20.GSR = "ENABLED";
    FD1S3IX cnt_n_2275__i21 (.D(n77[21]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[21])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i21.GSR = "ENABLED";
    FD1S3IX cnt_n_2275__i22 (.D(n77[22]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[22])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i22.GSR = "ENABLED";
    FD1S3IX cnt_n_2275__i23 (.D(n77[23]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[23])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i23.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i1 (.D(n77_adj_1665[1]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i1.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i2 (.D(n77_adj_1665[2]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i2.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i3 (.D(n77_adj_1665[3]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i3.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i4 (.D(n77_adj_1665[4]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i4.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i5 (.D(n77_adj_1665[5]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i5.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i6 (.D(n77_adj_1665[6]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i6.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i7 (.D(n77_adj_1665[7]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[7])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i7.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i8 (.D(n77_adj_1665[8]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[8])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i8.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i9 (.D(n77_adj_1665[9]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[9])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i9.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i10 (.D(n77_adj_1665[10]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[10])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i10.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i11 (.D(n77_adj_1665[11]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[11])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i11.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i12 (.D(n77_adj_1665[12]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[12])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i12.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i13 (.D(n77_adj_1665[13]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[13])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i13.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i14 (.D(n77_adj_1665[14]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[14])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i14.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i15 (.D(n77_adj_1665[15]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[15])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i15.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i16 (.D(n77_adj_1665[16]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[16])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i16.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i17 (.D(n77_adj_1665[17]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[17])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i17.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i18 (.D(n77_adj_1665[18]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[18])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i18.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i19 (.D(n77_adj_1665[19]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[19])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i19.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i20 (.D(n77_adj_1665[20]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[20])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i20.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i21 (.D(n77_adj_1665[21]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[21])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i21.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i22 (.D(n77_adj_1665[22]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[22])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i22.GSR = "ENABLED";
    FD1S3IX cnt_p_2276__i23 (.D(n77_adj_1665[23]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[23])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i23.GSR = "ENABLED";
    LUT4 i15353_4_lut (.A(cnt_p[22]), .B(cnt_p[23]), .C(n25173), .D(cnt_p[21]), 
         .Z(clk_p_N_959)) /* synthesis lut_function=(A (B+(C+(D)))+!A (B)) */ ;
    defparam i15353_4_lut.init = 16'heeec;
    LUT4 i2_4_lut (.A(cnt_p[18]), .B(cnt_p[19]), .C(n25194), .D(cnt_p[20]), 
         .Z(n25173)) /* synthesis lut_function=(A (B (D))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(27[19:24])
    defparam i2_4_lut.init = 16'hc800;
    LUT4 i3_4_lut_adj_39 (.A(n29687), .B(n6), .C(cnt_p[16]), .D(n4), 
         .Z(n25194)) /* synthesis lut_function=(A (B (C))+!A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(27[19:24])
    defparam i3_4_lut_adj_39.init = 16'hc080;
    LUT4 i2_2_lut_adj_40 (.A(cnt_p[15]), .B(cnt_p[17]), .Z(n6)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(27[19:24])
    defparam i2_2_lut_adj_40.init = 16'h8888;
    LUT4 i1_4_lut (.A(cnt_p[12]), .B(cnt_p[11]), .C(n21337), .D(cnt_p[10]), 
         .Z(n4)) /* synthesis lut_function=(A+(B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(27[19:24])
    defparam i1_4_lut.init = 16'heaaa;
    LUT4 i15290_4_lut (.A(n25414), .B(cnt_p[9]), .C(cnt_p[8]), .D(cnt_p[7]), 
         .Z(n21337)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i15290_4_lut.init = 16'hfcec;
    LUT4 i6_4_lut (.A(cnt_p[6]), .B(n12_adj_1662), .C(cnt_p[0]), .D(cnt_p[5]), 
         .Z(n25414)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam i6_4_lut.init = 16'h8000;
    LUT4 i5_4_lut_adj_41 (.A(cnt_p[3]), .B(cnt_p[2]), .C(cnt_p[4]), .D(cnt_p[1]), 
         .Z(n12_adj_1662)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam i5_4_lut_adj_41.init = 16'h8000;
    LUT4 sys_rst_n_I_0_1_lut (.A(sys_rst_n_c), .Z(sys_rst_n_N_484)) /* synthesis lut_function=(!(A)) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(74[9:19])
    defparam sys_rst_n_I_0_1_lut.init = 16'h5555;
    LUT4 i15274_4_lut (.A(n25253), .B(cnt_n[23]), .C(cnt_n[22]), .D(cnt_n[21]), 
         .Z(clk_n_N_962)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i15274_4_lut.init = 16'hfcec;
    LUT4 i2_4_lut_adj_42 (.A(cnt_n[20]), .B(n27569), .C(cnt_n[19]), .D(cnt_n[18]), 
         .Z(n25253)) /* synthesis lut_function=(A (B (C)+!B (C (D)))) */ ;
    defparam i2_4_lut_adj_42.init = 16'ha080;
    LUT4 i2_4_lut_adj_43 (.A(n27568), .B(n5), .C(cnt_n[15]), .D(n6_adj_1663), 
         .Z(n27569)) /* synthesis lut_function=(A (B (C)+!B (C (D)))) */ ;
    defparam i2_4_lut_adj_43.init = 16'ha080;
    LUT4 i1_2_lut (.A(cnt_n[12]), .B(cnt_n[13]), .Z(n5)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i1_2_lut.init = 16'heeee;
    LUT4 i2_4_lut_adj_44 (.A(cnt_n[11]), .B(cnt_n[14]), .C(n21339), .D(cnt_n[10]), 
         .Z(n6_adj_1663)) /* synthesis lut_function=(A (B+(C (D)))+!A (B)) */ ;
    defparam i2_4_lut_adj_44.init = 16'heccc;
    LUT4 i15292_4_lut (.A(n27443), .B(cnt_n[9]), .C(cnt_n[8]), .D(cnt_n[7]), 
         .Z(n21339)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i15292_4_lut.init = 16'hfcec;
    LUT4 i3_4_lut_adj_45 (.A(cnt_n[0]), .B(cnt_n[5]), .C(cnt_n[2]), .D(n27441), 
         .Z(n27443)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i3_4_lut_adj_45.init = 16'h8000;
    LUT4 i3_4_lut_adj_46 (.A(cnt_n[3]), .B(cnt_n[1]), .C(cnt_n[6]), .D(cnt_n[4]), 
         .Z(n27441)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i3_4_lut_adj_46.init = 16'h8000;
    LUT4 i1_2_lut_adj_47 (.A(cnt_n[16]), .B(cnt_n[17]), .Z(n27568)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_adj_47.init = 16'h8888;
    LUT4 clk_p_I_0_2_lut (.A(clk_p), .B(clk_n), .Z(clock)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(73[43:56])
    defparam clk_p_I_0_2_lut.init = 16'h8888;
    CCU2D cnt_p_2276_add_4_25 (.A0(cnt_p[23]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n25027), .S0(n77_adj_1665[23]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276_add_4_25.INIT0 = 16'hfaaa;
    defparam cnt_p_2276_add_4_25.INIT1 = 16'h0000;
    defparam cnt_p_2276_add_4_25.INJECT1_0 = "NO";
    defparam cnt_p_2276_add_4_25.INJECT1_1 = "NO";
    CCU2D cnt_p_2276_add_4_23 (.A0(cnt_p[21]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_p[22]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25026), .COUT(n25027), .S0(n77_adj_1665[21]), 
          .S1(n77_adj_1665[22]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276_add_4_23.INIT0 = 16'hfaaa;
    defparam cnt_p_2276_add_4_23.INIT1 = 16'hfaaa;
    defparam cnt_p_2276_add_4_23.INJECT1_0 = "NO";
    defparam cnt_p_2276_add_4_23.INJECT1_1 = "NO";
    CCU2D cnt_p_2276_add_4_21 (.A0(cnt_p[19]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_p[20]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25025), .COUT(n25026), .S0(n77_adj_1665[19]), 
          .S1(n77_adj_1665[20]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276_add_4_21.INIT0 = 16'hfaaa;
    defparam cnt_p_2276_add_4_21.INIT1 = 16'hfaaa;
    defparam cnt_p_2276_add_4_21.INJECT1_0 = "NO";
    defparam cnt_p_2276_add_4_21.INJECT1_1 = "NO";
    FD1S3IX cnt_p_2276__i0 (.D(n77_adj_1665[0]), .CK(sys_clk_c), .CD(n16622), 
            .Q(cnt_p[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276__i0.GSR = "ENABLED";
    CCU2D cnt_p_2276_add_4_19 (.A0(cnt_p[17]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_p[18]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25024), .COUT(n25025), .S0(n77_adj_1665[17]), 
          .S1(n77_adj_1665[18]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276_add_4_19.INIT0 = 16'hfaaa;
    defparam cnt_p_2276_add_4_19.INIT1 = 16'hfaaa;
    defparam cnt_p_2276_add_4_19.INJECT1_0 = "NO";
    defparam cnt_p_2276_add_4_19.INJECT1_1 = "NO";
    CCU2D cnt_p_2276_add_4_17 (.A0(cnt_p[15]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_p[16]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25023), .COUT(n25024), .S0(n77_adj_1665[15]), 
          .S1(n77_adj_1665[16]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276_add_4_17.INIT0 = 16'hfaaa;
    defparam cnt_p_2276_add_4_17.INIT1 = 16'hfaaa;
    defparam cnt_p_2276_add_4_17.INJECT1_0 = "NO";
    defparam cnt_p_2276_add_4_17.INJECT1_1 = "NO";
    CCU2D cnt_p_2276_add_4_15 (.A0(cnt_p[13]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_p[14]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25022), .COUT(n25023), .S0(n77_adj_1665[13]), 
          .S1(n77_adj_1665[14]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276_add_4_15.INIT0 = 16'hfaaa;
    defparam cnt_p_2276_add_4_15.INIT1 = 16'hfaaa;
    defparam cnt_p_2276_add_4_15.INJECT1_0 = "NO";
    defparam cnt_p_2276_add_4_15.INJECT1_1 = "NO";
    FD1S3IX cnt_n_2275__i0 (.D(n77[0]), .CK(sys_clk_N_7), .CD(n16621), 
            .Q(cnt_n[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275__i0.GSR = "ENABLED";
    CCU2D cnt_p_2276_add_4_13 (.A0(cnt_p[11]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_p[12]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25021), .COUT(n25022), .S0(n77_adj_1665[11]), 
          .S1(n77_adj_1665[12]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276_add_4_13.INIT0 = 16'hfaaa;
    defparam cnt_p_2276_add_4_13.INIT1 = 16'hfaaa;
    defparam cnt_p_2276_add_4_13.INJECT1_0 = "NO";
    defparam cnt_p_2276_add_4_13.INJECT1_1 = "NO";
    CCU2D cnt_p_2276_add_4_11 (.A0(cnt_p[9]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_p[10]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25020), .COUT(n25021), .S0(n77_adj_1665[9]), 
          .S1(n77_adj_1665[10]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276_add_4_11.INIT0 = 16'hfaaa;
    defparam cnt_p_2276_add_4_11.INIT1 = 16'hfaaa;
    defparam cnt_p_2276_add_4_11.INJECT1_0 = "NO";
    defparam cnt_p_2276_add_4_11.INJECT1_1 = "NO";
    CCU2D cnt_p_2276_add_4_9 (.A0(cnt_p[7]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_p[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n25019), .COUT(n25020), .S0(n77_adj_1665[7]), .S1(n77_adj_1665[8]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276_add_4_9.INIT0 = 16'hfaaa;
    defparam cnt_p_2276_add_4_9.INIT1 = 16'hfaaa;
    defparam cnt_p_2276_add_4_9.INJECT1_0 = "NO";
    defparam cnt_p_2276_add_4_9.INJECT1_1 = "NO";
    CCU2D cnt_p_2276_add_4_7 (.A0(cnt_p[5]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_p[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n25018), .COUT(n25019), .S0(n77_adj_1665[5]), .S1(n77_adj_1665[6]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276_add_4_7.INIT0 = 16'hfaaa;
    defparam cnt_p_2276_add_4_7.INIT1 = 16'hfaaa;
    defparam cnt_p_2276_add_4_7.INJECT1_0 = "NO";
    defparam cnt_p_2276_add_4_7.INJECT1_1 = "NO";
    CCU2D cnt_p_2276_add_4_5 (.A0(cnt_p[3]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_p[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n25017), .COUT(n25018), .S0(n77_adj_1665[3]), .S1(n77_adj_1665[4]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276_add_4_5.INIT0 = 16'hfaaa;
    defparam cnt_p_2276_add_4_5.INIT1 = 16'hfaaa;
    defparam cnt_p_2276_add_4_5.INJECT1_0 = "NO";
    defparam cnt_p_2276_add_4_5.INJECT1_1 = "NO";
    CCU2D cnt_p_2276_add_4_3 (.A0(cnt_p[1]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_p[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n25016), .COUT(n25017), .S0(n77_adj_1665[1]), .S1(n77_adj_1665[2]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276_add_4_3.INIT0 = 16'hfaaa;
    defparam cnt_p_2276_add_4_3.INIT1 = 16'hfaaa;
    defparam cnt_p_2276_add_4_3.INJECT1_0 = "NO";
    defparam cnt_p_2276_add_4_3.INJECT1_1 = "NO";
    CCU2D cnt_p_2276_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_p[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .COUT(n25016), .S1(n77_adj_1665[0]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(38[16:23])
    defparam cnt_p_2276_add_4_1.INIT0 = 16'hF000;
    defparam cnt_p_2276_add_4_1.INIT1 = 16'h0555;
    defparam cnt_p_2276_add_4_1.INJECT1_0 = "NO";
    defparam cnt_p_2276_add_4_1.INJECT1_1 = "NO";
    CCU2D cnt_n_2275_add_4_25 (.A0(cnt_n[23]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n25015), .S0(n77[23]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275_add_4_25.INIT0 = 16'hfaaa;
    defparam cnt_n_2275_add_4_25.INIT1 = 16'h0000;
    defparam cnt_n_2275_add_4_25.INJECT1_0 = "NO";
    defparam cnt_n_2275_add_4_25.INJECT1_1 = "NO";
    CCU2D cnt_n_2275_add_4_23 (.A0(cnt_n[21]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_n[22]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25014), .COUT(n25015), .S0(n77[21]), .S1(n77[22]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275_add_4_23.INIT0 = 16'hfaaa;
    defparam cnt_n_2275_add_4_23.INIT1 = 16'hfaaa;
    defparam cnt_n_2275_add_4_23.INJECT1_0 = "NO";
    defparam cnt_n_2275_add_4_23.INJECT1_1 = "NO";
    CCU2D cnt_n_2275_add_4_21 (.A0(cnt_n[19]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_n[20]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25013), .COUT(n25014), .S0(n77[19]), .S1(n77[20]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275_add_4_21.INIT0 = 16'hfaaa;
    defparam cnt_n_2275_add_4_21.INIT1 = 16'hfaaa;
    defparam cnt_n_2275_add_4_21.INJECT1_0 = "NO";
    defparam cnt_n_2275_add_4_21.INJECT1_1 = "NO";
    CCU2D cnt_n_2275_add_4_19 (.A0(cnt_n[17]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_n[18]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25012), .COUT(n25013), .S0(n77[17]), .S1(n77[18]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275_add_4_19.INIT0 = 16'hfaaa;
    defparam cnt_n_2275_add_4_19.INIT1 = 16'hfaaa;
    defparam cnt_n_2275_add_4_19.INJECT1_0 = "NO";
    defparam cnt_n_2275_add_4_19.INJECT1_1 = "NO";
    CCU2D cnt_n_2275_add_4_17 (.A0(cnt_n[15]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_n[16]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25011), .COUT(n25012), .S0(n77[15]), .S1(n77[16]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275_add_4_17.INIT0 = 16'hfaaa;
    defparam cnt_n_2275_add_4_17.INIT1 = 16'hfaaa;
    defparam cnt_n_2275_add_4_17.INJECT1_0 = "NO";
    defparam cnt_n_2275_add_4_17.INJECT1_1 = "NO";
    CCU2D cnt_n_2275_add_4_15 (.A0(cnt_n[13]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_n[14]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25010), .COUT(n25011), .S0(n77[13]), .S1(n77[14]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275_add_4_15.INIT0 = 16'hfaaa;
    defparam cnt_n_2275_add_4_15.INIT1 = 16'hfaaa;
    defparam cnt_n_2275_add_4_15.INJECT1_0 = "NO";
    defparam cnt_n_2275_add_4_15.INJECT1_1 = "NO";
    CCU2D cnt_n_2275_add_4_13 (.A0(cnt_n[11]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_n[12]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25009), .COUT(n25010), .S0(n77[11]), .S1(n77[12]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275_add_4_13.INIT0 = 16'hfaaa;
    defparam cnt_n_2275_add_4_13.INIT1 = 16'hfaaa;
    defparam cnt_n_2275_add_4_13.INJECT1_0 = "NO";
    defparam cnt_n_2275_add_4_13.INJECT1_1 = "NO";
    CCU2D cnt_n_2275_add_4_11 (.A0(cnt_n[9]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_n[10]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25008), .COUT(n25009), .S0(n77[9]), .S1(n77[10]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275_add_4_11.INIT0 = 16'hfaaa;
    defparam cnt_n_2275_add_4_11.INIT1 = 16'hfaaa;
    defparam cnt_n_2275_add_4_11.INJECT1_0 = "NO";
    defparam cnt_n_2275_add_4_11.INJECT1_1 = "NO";
    CCU2D cnt_n_2275_add_4_9 (.A0(cnt_n[7]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_n[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n25007), .COUT(n25008), .S0(n77[7]), .S1(n77[8]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275_add_4_9.INIT0 = 16'hfaaa;
    defparam cnt_n_2275_add_4_9.INIT1 = 16'hfaaa;
    defparam cnt_n_2275_add_4_9.INJECT1_0 = "NO";
    defparam cnt_n_2275_add_4_9.INJECT1_1 = "NO";
    CCU2D cnt_n_2275_add_4_7 (.A0(cnt_n[5]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_n[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n25006), .COUT(n25007), .S0(n77[5]), .S1(n77[6]));   // f:/git/my/fpga/training_v2.0/code/clock/clock.v(59[16:23])
    defparam cnt_n_2275_add_4_7.INIT0 = 16'hfaaa;
    defparam cnt_n_2275_add_4_7.INIT1 = 16'hfaaa;
    defparam cnt_n_2275_add_4_7.INJECT1_0 = "NO";
    defparam cnt_n_2275_add_4_7.INJECT1_1 = "NO";
    
endmodule
//
// Verilog Description of module \uart_send(CLK_FREQ=12000000,UART_BPS=115200) 
//

module \uart_send(CLK_FREQ=12000000,UART_BPS=115200)  (sys_clk_c, \usart_send_state_31__N_281[1] , 
            uart_en_w, uart_tx_bus_c, n29694, \usart_send_state[1] , 
            usart_send_state_31__N_277, n29668, uart_data_w, \usart_send_cnt[2] , 
            \usart_send_cnt[1] , \usart_send_cnt[0] , n29669, \temperature_data[5] , 
            n27426, sys_clk_c_enable_77, n16624, GND_net, n8730, n27541, 
            \uart_data_w_7__N_345[7] , \temperature_data[7] , n16625, 
            \usart_send_state[0] , n8, \uart_data_w_7__N_345[5] , n1130, 
            \uart_data_w_7__N_345[4] , n4919, clock_flag, \uart_data_w_7__N_345[2] , 
            n4920, \uart_data_w_7__N_345[1] ) /* synthesis syn_module_defined=1 */ ;
    input sys_clk_c;
    output \usart_send_state_31__N_281[1] ;
    input uart_en_w;
    output uart_tx_bus_c;
    input n29694;
    input \usart_send_state[1] ;
    input usart_send_state_31__N_277;
    output n29668;
    input [7:0]uart_data_w;
    input \usart_send_cnt[2] ;
    input \usart_send_cnt[1] ;
    input \usart_send_cnt[0] ;
    output n29669;
    input \temperature_data[5] ;
    output n27426;
    output sys_clk_c_enable_77;
    input n16624;
    input GND_net;
    output n8730;
    input n27541;
    output \uart_data_w_7__N_345[7] ;
    input \temperature_data[7] ;
    input n16625;
    input \usart_send_state[0] ;
    input n8;
    output \uart_data_w_7__N_345[5] ;
    input n1130;
    output \uart_data_w_7__N_345[4] ;
    input n4919;
    input clock_flag;
    output \uart_data_w_7__N_345[2] ;
    input n4920;
    output \uart_data_w_7__N_345[1] ;
    
    wire sys_clk_c /* synthesis SET_AS_NETWORK=sys_clk_c, is_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(12[19:26])
    
    wire uart_en_d1, uart_en_d0, n16573, uart_txd_N_526, n9038;
    wire [7:0]tx_data;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(49[12:19])
    wire [15:0]n2245;
    
    wire n9039, n42, n28099, n14101;
    wire [0:0]n4153;
    
    wire n13804, n9;
    wire [15:0]clk_cnt;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(46[12:19])
    
    wire n8_c, n185, tx_flag_N_530, n27728, n27925, n13, n14, 
        n28102;
    wire [0:0]n4182;
    
    wire n9030, n25303, n10, sys_clk_c_enable_124, n23635;
    wire [15:0]n69;
    
    wire n14100, n25356, n4, n25039, n25038, n25037, n25036, n28091, 
        n25035, n25034, n25033, n25032, n8_adj_1636;
    
    FD1S3AX uart_en_d1_38 (.D(uart_en_d0), .CK(sys_clk_c), .Q(uart_en_d1)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=352, LSE_RLINE=360 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(66[10] 69[8])
    defparam uart_en_d1_38.GSR = "ENABLED";
    FD1S3AX tx_flag_39 (.D(n16573), .CK(sys_clk_c), .Q(\usart_send_state_31__N_281[1] )) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=352, LSE_RLINE=360 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(78[10] 91[12])
    defparam tx_flag_39.GSR = "ENABLED";
    FD1S3AX uart_en_d0_37 (.D(uart_en_w), .CK(sys_clk_c), .Q(uart_en_d0)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=352, LSE_RLINE=360 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(66[10] 69[8])
    defparam uart_en_d0_37.GSR = "ENABLED";
    FD1S3JX uart_txd_44 (.D(uart_txd_N_526), .CK(sys_clk_c), .PD(n29694), 
            .Q(uart_tx_bus_c)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=352, LSE_RLINE=360 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(120[10] 135[26])
    defparam uart_txd_44.GSR = "ENABLED";
    LUT4 i3510_3_lut (.A(n9038), .B(tx_data[4]), .C(n2245[5]), .Z(n9039)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(121[9] 133[16])
    defparam i3510_3_lut.init = 16'hcaca;
    LUT4 i1_2_lut_rep_392 (.A(\usart_send_state[1] ), .B(usart_send_state_31__N_277), 
         .Z(n29668)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(245[11:27])
    defparam i1_2_lut_rep_392.init = 16'heeee;
    LUT4 i1_2_lut_3_lut (.A(\usart_send_state[1] ), .B(usart_send_state_31__N_277), 
         .C(uart_data_w[2]), .Z(n42)) /* synthesis lut_function=(A (C)+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(245[11:27])
    defparam i1_2_lut_3_lut.init = 16'he0e0;
    LUT4 i2_3_lut_rep_393 (.A(\usart_send_cnt[2] ), .B(\usart_send_cnt[1] ), 
         .C(\usart_send_cnt[0] ), .Z(n29669)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(245[11:27])
    defparam i2_3_lut_rep_393.init = 16'h4040;
    LUT4 i1_2_lut_4_lut (.A(\usart_send_cnt[2] ), .B(\usart_send_cnt[1] ), 
         .C(\usart_send_cnt[0] ), .D(\temperature_data[5] ), .Z(n27426)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(245[11:27])
    defparam i1_2_lut_4_lut.init = 16'h4000;
    FD1P3JX tx_cnt_FSM_i0 (.D(n2245[15]), .SP(sys_clk_c_enable_77), .PD(n29694), 
            .CK(sys_clk_c), .Q(n2245[0]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(107[24:37])
    defparam tx_cnt_FSM_i0.GSR = "ENABLED";
    LUT4 i22061_4_lut_4_lut (.A(n2245[8]), .B(n28099), .C(n14101), .D(n4153[0]), 
         .Z(n13804)) /* synthesis lut_function=(A (C)+!A (B (D)+!B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(107[24:37])
    defparam i22061_4_lut_4_lut.init = 16'hf4b0;
    LUT4 i5_4_lut (.A(n9), .B(clk_cnt[6]), .C(n8_c), .D(clk_cnt[1]), 
         .Z(n185)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i5_4_lut.init = 16'hfffe;
    LUT4 i3_4_lut (.A(tx_flag_N_530), .B(n27728), .C(n27925), .D(clk_cnt[5]), 
         .Z(n9)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ;
    defparam i3_4_lut.init = 16'hdfff;
    LUT4 i2_2_lut (.A(clk_cnt[0]), .B(clk_cnt[3]), .Z(n8_c)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i2_2_lut.init = 16'heeee;
    LUT4 i21779_2_lut (.A(clk_cnt[4]), .B(clk_cnt[2]), .Z(n27925)) /* synthesis lut_function=(A (B)) */ ;
    defparam i21779_2_lut.init = 16'h8888;
    LUT4 i1_3_lut (.A(clk_cnt[7]), .B(n13), .C(n14), .Z(n27728)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(46[12:19])
    defparam i1_3_lut.init = 16'hfefe;
    LUT4 i5_4_lut_adj_28 (.A(clk_cnt[11]), .B(clk_cnt[14]), .C(clk_cnt[15]), 
         .D(clk_cnt[12]), .Z(n13)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(46[12:19])
    defparam i5_4_lut_adj_28.init = 16'hfffe;
    LUT4 i6_4_lut (.A(clk_cnt[10]), .B(clk_cnt[13]), .C(clk_cnt[9]), .D(clk_cnt[8]), 
         .Z(n14)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(46[12:19])
    defparam i6_4_lut.init = 16'hfffe;
    PFUMX i7439 (.BLUT(n9039), .ALUT(n13804), .C0(n28102), .Z(n4182[0]));
    LUT4 i14593_4_lut (.A(n9030), .B(n2245[0]), .C(uart_tx_bus_c), .D(n25303), 
         .Z(uart_txd_N_526)) /* synthesis lut_function=(!(A (B+!(C+!(D)))+!A (B+!(C (D))))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(121[9] 133[16])
    defparam i14593_4_lut.init = 16'h3022;
    LUT4 i14799_2_lut (.A(n4182[0]), .B(tx_flag_N_530), .Z(n9030)) /* synthesis lut_function=(A+(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(121[9] 133[16])
    defparam i14799_2_lut.init = 16'heeee;
    FD1P3IX tx_cnt_FSM_i1 (.D(n2245[0]), .SP(sys_clk_c_enable_77), .CD(n29694), 
            .CK(sys_clk_c), .Q(n2245[1]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(107[24:37])
    defparam tx_cnt_FSM_i1.GSR = "ENABLED";
    LUT4 i5_3_lut (.A(n2245[15]), .B(n10), .C(n2245[13]), .Z(n25303)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(121[9] 133[16])
    defparam i5_3_lut.init = 16'hfefe;
    LUT4 i4_4_lut (.A(n2245[14]), .B(n2245[12]), .C(n2245[11]), .D(n2245[10]), 
         .Z(n10)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(121[9] 133[16])
    defparam i4_4_lut.init = 16'hfffe;
    FD1P3IX tx_cnt_FSM_i2 (.D(n2245[1]), .SP(sys_clk_c_enable_77), .CD(n29694), 
            .CK(sys_clk_c), .Q(n2245[2]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(107[24:37])
    defparam tx_cnt_FSM_i2.GSR = "ENABLED";
    FD1P3IX tx_cnt_FSM_i3 (.D(n2245[2]), .SP(sys_clk_c_enable_77), .CD(n29694), 
            .CK(sys_clk_c), .Q(n2245[3]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(107[24:37])
    defparam tx_cnt_FSM_i3.GSR = "ENABLED";
    FD1P3IX tx_cnt_FSM_i4 (.D(n2245[3]), .SP(sys_clk_c_enable_77), .CD(n29694), 
            .CK(sys_clk_c), .Q(n2245[4]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(107[24:37])
    defparam tx_cnt_FSM_i4.GSR = "ENABLED";
    FD1P3IX tx_cnt_FSM_i5 (.D(n2245[4]), .SP(sys_clk_c_enable_77), .CD(n29694), 
            .CK(sys_clk_c), .Q(n2245[5]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(107[24:37])
    defparam tx_cnt_FSM_i5.GSR = "ENABLED";
    FD1P3IX tx_cnt_FSM_i6 (.D(n2245[5]), .SP(sys_clk_c_enable_77), .CD(n29694), 
            .CK(sys_clk_c), .Q(n2245[6]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(107[24:37])
    defparam tx_cnt_FSM_i6.GSR = "ENABLED";
    FD1P3IX tx_cnt_FSM_i7 (.D(n2245[6]), .SP(sys_clk_c_enable_77), .CD(n29694), 
            .CK(sys_clk_c), .Q(n2245[7]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(107[24:37])
    defparam tx_cnt_FSM_i7.GSR = "ENABLED";
    FD1P3IX tx_cnt_FSM_i8 (.D(n2245[7]), .SP(sys_clk_c_enable_77), .CD(n29694), 
            .CK(sys_clk_c), .Q(n2245[8]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(107[24:37])
    defparam tx_cnt_FSM_i8.GSR = "ENABLED";
    FD1P3IX tx_cnt_FSM_i9 (.D(n2245[8]), .SP(sys_clk_c_enable_77), .CD(n29694), 
            .CK(sys_clk_c), .Q(tx_flag_N_530));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(107[24:37])
    defparam tx_cnt_FSM_i9.GSR = "ENABLED";
    FD1P3IX tx_cnt_FSM_i10 (.D(tx_flag_N_530), .SP(sys_clk_c_enable_77), 
            .CD(n29694), .CK(sys_clk_c), .Q(n2245[10]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(107[24:37])
    defparam tx_cnt_FSM_i10.GSR = "ENABLED";
    FD1P3IX tx_cnt_FSM_i11 (.D(n2245[10]), .SP(sys_clk_c_enable_77), .CD(n29694), 
            .CK(sys_clk_c), .Q(n2245[11]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(107[24:37])
    defparam tx_cnt_FSM_i11.GSR = "ENABLED";
    FD1P3IX tx_cnt_FSM_i12 (.D(n2245[11]), .SP(sys_clk_c_enable_77), .CD(n29694), 
            .CK(sys_clk_c), .Q(n2245[12]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(107[24:37])
    defparam tx_cnt_FSM_i12.GSR = "ENABLED";
    FD1P3IX tx_cnt_FSM_i13 (.D(n2245[12]), .SP(sys_clk_c_enable_77), .CD(n29694), 
            .CK(sys_clk_c), .Q(n2245[13]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(107[24:37])
    defparam tx_cnt_FSM_i13.GSR = "ENABLED";
    FD1P3IX tx_cnt_FSM_i14 (.D(n2245[13]), .SP(sys_clk_c_enable_77), .CD(n29694), 
            .CK(sys_clk_c), .Q(n2245[14]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(107[24:37])
    defparam tx_cnt_FSM_i14.GSR = "ENABLED";
    FD1P3IX tx_cnt_FSM_i15 (.D(n2245[14]), .SP(sys_clk_c_enable_77), .CD(n29694), 
            .CK(sys_clk_c), .Q(n2245[15]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(107[24:37])
    defparam tx_cnt_FSM_i15.GSR = "ENABLED";
    FD1P3IX tx_data_i1 (.D(uart_data_w[1]), .SP(sys_clk_c_enable_124), .CD(n23635), 
            .CK(sys_clk_c), .Q(tx_data[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=352, LSE_RLINE=360 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(78[10] 91[12])
    defparam tx_data_i1.GSR = "ENABLED";
    FD1P3IX tx_data_i2 (.D(uart_data_w[2]), .SP(sys_clk_c_enable_124), .CD(n23635), 
            .CK(sys_clk_c), .Q(tx_data[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=352, LSE_RLINE=360 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(78[10] 91[12])
    defparam tx_data_i2.GSR = "ENABLED";
    FD1P3IX tx_data_i3 (.D(uart_data_w[3]), .SP(sys_clk_c_enable_124), .CD(n23635), 
            .CK(sys_clk_c), .Q(tx_data[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=352, LSE_RLINE=360 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(78[10] 91[12])
    defparam tx_data_i3.GSR = "ENABLED";
    FD1P3IX tx_data_i4 (.D(uart_data_w[4]), .SP(sys_clk_c_enable_124), .CD(n23635), 
            .CK(sys_clk_c), .Q(tx_data[4])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=352, LSE_RLINE=360 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(78[10] 91[12])
    defparam tx_data_i4.GSR = "ENABLED";
    FD1P3IX tx_data_i5 (.D(uart_data_w[5]), .SP(sys_clk_c_enable_124), .CD(n23635), 
            .CK(sys_clk_c), .Q(tx_data[5])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=352, LSE_RLINE=360 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(78[10] 91[12])
    defparam tx_data_i5.GSR = "ENABLED";
    FD1P3IX tx_data_i6 (.D(uart_data_w[6]), .SP(sys_clk_c_enable_124), .CD(n23635), 
            .CK(sys_clk_c), .Q(tx_data[6])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=352, LSE_RLINE=360 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(78[10] 91[12])
    defparam tx_data_i6.GSR = "ENABLED";
    FD1P3IX tx_data_i7 (.D(uart_data_w[7]), .SP(sys_clk_c_enable_124), .CD(n23635), 
            .CK(sys_clk_c), .Q(tx_data[7])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=352, LSE_RLINE=360 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(78[10] 91[12])
    defparam tx_data_i7.GSR = "ENABLED";
    FD1S3IX clk_cnt_2270__i1 (.D(n69[1]), .CK(sys_clk_c), .CD(n16624), 
            .Q(clk_cnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270__i1.GSR = "ENABLED";
    FD1S3IX clk_cnt_2270__i2 (.D(n69[2]), .CK(sys_clk_c), .CD(n16624), 
            .Q(clk_cnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270__i2.GSR = "ENABLED";
    FD1S3IX clk_cnt_2270__i3 (.D(n69[3]), .CK(sys_clk_c), .CD(n16624), 
            .Q(clk_cnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270__i3.GSR = "ENABLED";
    FD1S3IX clk_cnt_2270__i4 (.D(n69[4]), .CK(sys_clk_c), .CD(n16624), 
            .Q(clk_cnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270__i4.GSR = "ENABLED";
    FD1S3IX clk_cnt_2270__i5 (.D(n69[5]), .CK(sys_clk_c), .CD(n16624), 
            .Q(clk_cnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270__i5.GSR = "ENABLED";
    FD1S3IX clk_cnt_2270__i6 (.D(n69[6]), .CK(sys_clk_c), .CD(n16624), 
            .Q(clk_cnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270__i6.GSR = "ENABLED";
    FD1S3IX clk_cnt_2270__i7 (.D(n69[7]), .CK(sys_clk_c), .CD(n16624), 
            .Q(clk_cnt[7])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270__i7.GSR = "ENABLED";
    FD1S3IX clk_cnt_2270__i8 (.D(n69[8]), .CK(sys_clk_c), .CD(n16624), 
            .Q(clk_cnt[8])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270__i8.GSR = "ENABLED";
    FD1S3IX clk_cnt_2270__i9 (.D(n69[9]), .CK(sys_clk_c), .CD(n16624), 
            .Q(clk_cnt[9])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270__i9.GSR = "ENABLED";
    FD1S3IX clk_cnt_2270__i10 (.D(n69[10]), .CK(sys_clk_c), .CD(n16624), 
            .Q(clk_cnt[10])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270__i10.GSR = "ENABLED";
    FD1S3IX clk_cnt_2270__i11 (.D(n69[11]), .CK(sys_clk_c), .CD(n16624), 
            .Q(clk_cnt[11])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270__i11.GSR = "ENABLED";
    FD1S3IX clk_cnt_2270__i12 (.D(n69[12]), .CK(sys_clk_c), .CD(n16624), 
            .Q(clk_cnt[12])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270__i12.GSR = "ENABLED";
    FD1S3IX clk_cnt_2270__i13 (.D(n69[13]), .CK(sys_clk_c), .CD(n16624), 
            .Q(clk_cnt[13])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270__i13.GSR = "ENABLED";
    FD1S3IX clk_cnt_2270__i14 (.D(n69[14]), .CK(sys_clk_c), .CD(n16624), 
            .Q(clk_cnt[14])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270__i14.GSR = "ENABLED";
    FD1S3IX clk_cnt_2270__i15 (.D(n69[15]), .CK(sys_clk_c), .CD(n16624), 
            .Q(clk_cnt[15])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270__i15.GSR = "ENABLED";
    LUT4 i22278_2_lut_2_lut_3_lut (.A(uart_en_d0), .B(uart_en_d1), .C(n185), 
         .Z(n23635)) /* synthesis lut_function=(!(A ((C)+!B)+!A (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(66[10] 69[8])
    defparam i22278_2_lut_2_lut_3_lut.init = 16'h0d0d;
    LUT4 i1_3_lut_4_lut (.A(uart_en_d0), .B(uart_en_d1), .C(\usart_send_state_31__N_281[1] ), 
         .D(n185), .Z(n16573)) /* synthesis lut_function=(A ((C (D))+!B)+!A (C (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(66[10] 69[8])
    defparam i1_3_lut_4_lut.init = 16'hf222;
    LUT4 i1_2_lut_3_lut_adj_29 (.A(uart_en_d0), .B(uart_en_d1), .C(n185), 
         .Z(sys_clk_c_enable_124)) /* synthesis lut_function=(!(A (B (C))+!A (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(66[10] 69[8])
    defparam i1_2_lut_3_lut_adj_29.init = 16'h2f2f;
    LUT4 i8199_3_lut (.A(tx_data[5]), .B(tx_data[6]), .C(n2245[7]), .Z(n14100)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(121[9] 133[16])
    defparam i8199_3_lut.init = 16'hcaca;
    LUT4 i21948_2_lut (.A(n2245[7]), .B(n2245[6]), .Z(n28099)) /* synthesis lut_function=(!(A+(B))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(121[9] 133[16])
    defparam i21948_2_lut.init = 16'h1111;
    LUT4 i1_4_lut (.A(clk_cnt[6]), .B(n27728), .C(n25356), .D(clk_cnt[5]), 
         .Z(sys_clk_c_enable_77)) /* synthesis lut_function=(A (B+(C (D)))+!A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(46[12:19])
    defparam i1_4_lut.init = 16'heccc;
    LUT4 i2_4_lut (.A(clk_cnt[2]), .B(clk_cnt[4]), .C(n4), .D(clk_cnt[3]), 
         .Z(n25356)) /* synthesis lut_function=(A (B+(C+(D)))+!A (B+(D))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(46[12:19])
    defparam i2_4_lut.init = 16'hffec;
    LUT4 i1_2_lut (.A(clk_cnt[0]), .B(clk_cnt[1]), .Z(n4)) /* synthesis lut_function=(A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(46[12:19])
    defparam i1_2_lut.init = 16'h8888;
    CCU2D clk_cnt_2270_add_4_17 (.A0(clk_cnt[15]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n25039), .S0(n69[15]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270_add_4_17.INIT0 = 16'hfaaa;
    defparam clk_cnt_2270_add_4_17.INIT1 = 16'h0000;
    defparam clk_cnt_2270_add_4_17.INJECT1_0 = "NO";
    defparam clk_cnt_2270_add_4_17.INJECT1_1 = "NO";
    CCU2D clk_cnt_2270_add_4_15 (.A0(clk_cnt[13]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clk_cnt[14]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25038), .COUT(n25039), .S0(n69[13]), .S1(n69[14]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270_add_4_15.INIT0 = 16'hfaaa;
    defparam clk_cnt_2270_add_4_15.INIT1 = 16'hfaaa;
    defparam clk_cnt_2270_add_4_15.INJECT1_0 = "NO";
    defparam clk_cnt_2270_add_4_15.INJECT1_1 = "NO";
    LUT4 i1_3_lut_adj_30 (.A(\usart_send_state[1] ), .B(usart_send_state_31__N_277), 
         .C(\usart_send_state_31__N_281[1] ), .Z(n8730)) /* synthesis lut_function=(A (B+(C))+!A (B)) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(245[11:27])
    defparam i1_3_lut_adj_30.init = 16'hecec;
    CCU2D clk_cnt_2270_add_4_13 (.A0(clk_cnt[11]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clk_cnt[12]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25037), .COUT(n25038), .S0(n69[11]), .S1(n69[12]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270_add_4_13.INIT0 = 16'hfaaa;
    defparam clk_cnt_2270_add_4_13.INIT1 = 16'hfaaa;
    defparam clk_cnt_2270_add_4_13.INJECT1_0 = "NO";
    defparam clk_cnt_2270_add_4_13.INJECT1_1 = "NO";
    CCU2D clk_cnt_2270_add_4_11 (.A0(clk_cnt[9]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clk_cnt[10]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25036), .COUT(n25037), .S0(n69[9]), .S1(n69[10]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270_add_4_11.INIT0 = 16'hfaaa;
    defparam clk_cnt_2270_add_4_11.INIT1 = 16'hfaaa;
    defparam clk_cnt_2270_add_4_11.INJECT1_0 = "NO";
    defparam clk_cnt_2270_add_4_11.INJECT1_1 = "NO";
    LUT4 i3509_3_lut (.A(tx_data[2]), .B(tx_data[3]), .C(n2245[4]), .Z(n9038)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(121[9] 133[16])
    defparam i3509_3_lut.init = 16'hcaca;
    LUT4 i22245_4_lut (.A(n2245[8]), .B(n2245[7]), .C(n2245[6]), .D(n28091), 
         .Z(n28102)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(121[9] 133[16])
    defparam i22245_4_lut.init = 16'hfffe;
    CCU2D clk_cnt_2270_add_4_9 (.A0(clk_cnt[7]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clk_cnt[8]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25035), .COUT(n25036), .S0(n69[7]), .S1(n69[8]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270_add_4_9.INIT0 = 16'hfaaa;
    defparam clk_cnt_2270_add_4_9.INIT1 = 16'hfaaa;
    defparam clk_cnt_2270_add_4_9.INJECT1_0 = "NO";
    defparam clk_cnt_2270_add_4_9.INJECT1_1 = "NO";
    LUT4 i21940_3_lut (.A(n2245[5]), .B(n2245[4]), .C(n2245[3]), .Z(n28091)) /* synthesis lut_function=(!(A+(B+(C)))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(121[9] 133[16])
    defparam i21940_3_lut.init = 16'h0101;
    CCU2D clk_cnt_2270_add_4_7 (.A0(clk_cnt[5]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clk_cnt[6]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25034), .COUT(n25035), .S0(n69[5]), .S1(n69[6]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270_add_4_7.INIT0 = 16'hfaaa;
    defparam clk_cnt_2270_add_4_7.INIT1 = 16'hfaaa;
    defparam clk_cnt_2270_add_4_7.INJECT1_0 = "NO";
    defparam clk_cnt_2270_add_4_7.INJECT1_1 = "NO";
    CCU2D clk_cnt_2270_add_4_5 (.A0(clk_cnt[3]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clk_cnt[4]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25033), .COUT(n25034), .S0(n69[3]), .S1(n69[4]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270_add_4_5.INIT0 = 16'hfaaa;
    defparam clk_cnt_2270_add_4_5.INIT1 = 16'hfaaa;
    defparam clk_cnt_2270_add_4_5.INJECT1_0 = "NO";
    defparam clk_cnt_2270_add_4_5.INJECT1_1 = "NO";
    CCU2D clk_cnt_2270_add_4_3 (.A0(clk_cnt[1]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clk_cnt[2]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25032), .COUT(n25033), .S0(n69[1]), .S1(n69[2]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270_add_4_3.INIT0 = 16'hfaaa;
    defparam clk_cnt_2270_add_4_3.INIT1 = 16'hfaaa;
    defparam clk_cnt_2270_add_4_3.INJECT1_0 = "NO";
    defparam clk_cnt_2270_add_4_3.INJECT1_1 = "NO";
    CCU2D clk_cnt_2270_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(clk_cnt[0]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .COUT(n25032), .S1(n69[0]));   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270_add_4_1.INIT0 = 16'hF000;
    defparam clk_cnt_2270_add_4_1.INIT1 = 16'h0555;
    defparam clk_cnt_2270_add_4_1.INJECT1_0 = "NO";
    defparam clk_cnt_2270_add_4_1.INJECT1_1 = "NO";
    LUT4 i1_4_lut_adj_31 (.A(n29668), .B(n8_adj_1636), .C(uart_data_w[7]), 
         .D(n27541), .Z(\uart_data_w_7__N_345[7] )) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(245[11:27])
    defparam i1_4_lut_adj_31.init = 16'heca0;
    LUT4 i21_4_lut (.A(\temperature_data[7] ), .B(uart_data_w[7]), .C(n16625), 
         .D(n29669), .Z(n8_adj_1636)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(245[11:27])
    defparam i21_4_lut.init = 16'hcac0;
    FD1S3IX clk_cnt_2270__i0 (.D(n69[0]), .CK(sys_clk_c), .CD(n16624), 
            .Q(clk_cnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(102[24:38])
    defparam clk_cnt_2270__i0.GSR = "ENABLED";
    LUT4 i1_4_lut_adj_32 (.A(\usart_send_state[0] ), .B(n29668), .C(n8), 
         .D(uart_data_w[5]), .Z(\uart_data_w_7__N_345[5] )) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(245[11:27])
    defparam i1_4_lut_adj_32.init = 16'heca0;
    LUT4 i1_4_lut_adj_33 (.A(n1130), .B(n29668), .C(\usart_send_state[0] ), 
         .D(uart_data_w[4]), .Z(\uart_data_w_7__N_345[4] )) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(245[11:27])
    defparam i1_4_lut_adj_33.init = 16'heca0;
    LUT4 i1_4_lut_adj_34 (.A(n4919), .B(n42), .C(\usart_send_state[0] ), 
         .D(clock_flag), .Z(\uart_data_w_7__N_345[2] )) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(245[11:27])
    defparam i1_4_lut_adj_34.init = 16'hfcec;
    LUT4 i1_4_lut_adj_35 (.A(n4920), .B(n29668), .C(n27541), .D(uart_data_w[1]), 
         .Z(\uart_data_w_7__N_345[1] )) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(245[11:27])
    defparam i1_4_lut_adj_35.init = 16'heca0;
    FD1P3IX tx_data_i0 (.D(uart_data_w[0]), .SP(sys_clk_c_enable_124), .CD(n23635), 
            .CK(sys_clk_c), .Q(tx_data[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=1, LSE_RCOL=6, LSE_LLINE=352, LSE_RLINE=360 */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(78[10] 91[12])
    defparam tx_data_i0.GSR = "ENABLED";
    LUT4 i8200_3_lut (.A(n14100), .B(tx_data[7]), .C(n2245[8]), .Z(n14101)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(121[9] 133[16])
    defparam i8200_3_lut.init = 16'hcaca;
    LUT4 mux_1197_i1_3_lut (.A(tx_data[0]), .B(tx_data[1]), .C(n2245[2]), 
         .Z(n4153[0])) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/git/my/fpga/training_v2.0/code/uart/uart_send.v(121[9] 133[16])
    defparam mux_1197_i1_3_lut.init = 16'hcaca;
    
endmodule
//
// Verilog Description of module Beeper
//

module Beeper (BEEP_bus_c, sys_clk_c, Beep_status_uart, sys_rst_n_c, 
            GND_net, VCC_net, beep_en_reg) /* synthesis syn_module_defined=1 */ ;
    output BEEP_bus_c;
    input sys_clk_c;
    input [4:0]Beep_status_uart;
    input sys_rst_n_c;
    input GND_net;
    input VCC_net;
    input beep_en_reg;
    
    wire sys_clk_c /* synthesis SET_AS_NETWORK=sys_clk_c, is_clock=1 */ ;   // f:/git/my/fpga/training_v2.0/code/core/controller.v(12[19:26])
    
    wire piano_out_N_855;
    wire [15:0]time_end;   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(31[12:20])
    
    wire n25003;
    wire [17:0]time_cnt;   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(63[12:20])
    wire [17:0]n77;
    
    wire n2702, n25002, n25001, n25000, n24999, n24998, n24997, 
        n24996, n24995, n29, n34, n30;
    wire [17:0]n4252;
    
    wire n31, n28, n4271, n24976, n24975, n24974, n24973, n24972, 
        n24971, n24970, n24969, n24968;
    
    FD1S3AX piano_out_20 (.D(piano_out_N_855), .CK(sys_clk_c), .Q(BEEP_bus_c)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=9, LSE_RCOL=2, LSE_LLINE=408, LSE_RLINE=415 */ ;   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(81[11] 85[5])
    defparam piano_out_20.GSR = "ENABLED";
    PDPW8KC tone_4__I_0 (.DI0(GND_net), .DI1(GND_net), .DI2(GND_net), 
            .DI3(GND_net), .DI4(GND_net), .DI5(GND_net), .DI6(GND_net), 
            .DI7(GND_net), .DI8(GND_net), .DI9(GND_net), .DI10(GND_net), 
            .DI11(GND_net), .DI12(GND_net), .DI13(GND_net), .DI14(GND_net), 
            .DI15(GND_net), .DI16(GND_net), .DI17(GND_net), .ADW0(GND_net), 
            .ADW1(GND_net), .ADW2(GND_net), .ADW3(GND_net), .ADW4(GND_net), 
            .ADW5(GND_net), .ADW6(GND_net), .ADW7(GND_net), .ADW8(GND_net), 
            .BE0(GND_net), .BE1(GND_net), .CEW(VCC_net), .CLKW(GND_net), 
            .CSW0(GND_net), .CSW1(GND_net), .CSW2(GND_net), .ADR0(GND_net), 
            .ADR1(GND_net), .ADR2(GND_net), .ADR3(GND_net), .ADR4(Beep_status_uart[0]), 
            .ADR5(Beep_status_uart[1]), .ADR6(Beep_status_uart[2]), .ADR7(Beep_status_uart[3]), 
            .ADR8(Beep_status_uart[4]), .ADR9(GND_net), .ADR10(GND_net), 
            .ADR11(GND_net), .ADR12(GND_net), .CER(sys_rst_n_c), .OCER(VCC_net), 
            .CLKR(sys_clk_c), .CSR0(GND_net), .CSR1(GND_net), .CSR2(GND_net), 
            .RST(GND_net), .DO0(time_end[9]), .DO1(time_end[10]), .DO2(time_end[11]), 
            .DO3(time_end[12]), .DO4(time_end[13]), .DO5(time_end[14]), 
            .DO6(time_end[15]), .DO9(time_end[0]), .DO10(time_end[1]), 
            .DO11(time_end[2]), .DO12(time_end[3]), .DO13(time_end[4]), 
            .DO14(time_end[5]), .DO15(time_end[6]), .DO16(time_end[7]), 
            .DO17(time_end[8]));
    defparam tone_4__I_0.DATA_WIDTH_W = 18;
    defparam tone_4__I_0.DATA_WIDTH_R = 18;
    defparam tone_4__I_0.REGMODE = "NOREG";
    defparam tone_4__I_0.CSDECODE_W = "0b000";
    defparam tone_4__I_0.CSDECODE_R = "0b000";
    defparam tone_4__I_0.GSR = "DISABLED";
    defparam tone_4__I_0.RESETMODE = "ASYNC";
    defparam tone_4__I_0.ASYNC_RESET_RELEASE = "SYNC";
    defparam tone_4__I_0.INIT_DATA = "STATIC";
    defparam tone_4__I_0.INITVAL_00 = "0x0166C017B901AA101DE40218D0238C027E702CC802F730354303BC90431D0471B04FCC059970FFFF";
    defparam tone_4__I_0.INITVAL_01 = "0x0FFFF0FFFF0FFFF0FFFF0FFFF0FFFF0FFFF0FFFF0FFFF0FFFF00BDC00D5000EF1010C6011C5013F3";
    defparam tone_4__I_0.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    defparam tone_4__I_0.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
    CCU2D time_cnt_2274_add_4_19 (.A0(time_cnt[17]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n25003), .S0(n77[17]));   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274_add_4_19.INIT0 = 16'hfaaa;
    defparam time_cnt_2274_add_4_19.INIT1 = 16'h0000;
    defparam time_cnt_2274_add_4_19.INJECT1_0 = "NO";
    defparam time_cnt_2274_add_4_19.INJECT1_1 = "NO";
    FD1S3IX time_cnt_2274__i0 (.D(n77[0]), .CK(sys_clk_c), .CD(n2702), 
            .Q(time_cnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274__i0.GSR = "ENABLED";
    CCU2D time_cnt_2274_add_4_17 (.A0(time_cnt[15]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(time_cnt[16]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25002), .COUT(n25003), .S0(n77[15]), .S1(n77[16]));   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274_add_4_17.INIT0 = 16'hfaaa;
    defparam time_cnt_2274_add_4_17.INIT1 = 16'hfaaa;
    defparam time_cnt_2274_add_4_17.INJECT1_0 = "NO";
    defparam time_cnt_2274_add_4_17.INJECT1_1 = "NO";
    CCU2D time_cnt_2274_add_4_15 (.A0(time_cnt[13]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(time_cnt[14]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25001), .COUT(n25002), .S0(n77[13]), .S1(n77[14]));   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274_add_4_15.INIT0 = 16'hfaaa;
    defparam time_cnt_2274_add_4_15.INIT1 = 16'hfaaa;
    defparam time_cnt_2274_add_4_15.INJECT1_0 = "NO";
    defparam time_cnt_2274_add_4_15.INJECT1_1 = "NO";
    CCU2D time_cnt_2274_add_4_13 (.A0(time_cnt[11]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(time_cnt[12]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n25000), .COUT(n25001), .S0(n77[11]), .S1(n77[12]));   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274_add_4_13.INIT0 = 16'hfaaa;
    defparam time_cnt_2274_add_4_13.INIT1 = 16'hfaaa;
    defparam time_cnt_2274_add_4_13.INJECT1_0 = "NO";
    defparam time_cnt_2274_add_4_13.INJECT1_1 = "NO";
    CCU2D time_cnt_2274_add_4_11 (.A0(time_cnt[9]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(time_cnt[10]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24999), .COUT(n25000), .S0(n77[9]), .S1(n77[10]));   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274_add_4_11.INIT0 = 16'hfaaa;
    defparam time_cnt_2274_add_4_11.INIT1 = 16'hfaaa;
    defparam time_cnt_2274_add_4_11.INJECT1_0 = "NO";
    defparam time_cnt_2274_add_4_11.INJECT1_1 = "NO";
    CCU2D time_cnt_2274_add_4_9 (.A0(time_cnt[7]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(time_cnt[8]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24998), .COUT(n24999), .S0(n77[7]), .S1(n77[8]));   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274_add_4_9.INIT0 = 16'hfaaa;
    defparam time_cnt_2274_add_4_9.INIT1 = 16'hfaaa;
    defparam time_cnt_2274_add_4_9.INJECT1_0 = "NO";
    defparam time_cnt_2274_add_4_9.INJECT1_1 = "NO";
    CCU2D time_cnt_2274_add_4_7 (.A0(time_cnt[5]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(time_cnt[6]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24997), .COUT(n24998), .S0(n77[5]), .S1(n77[6]));   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274_add_4_7.INIT0 = 16'hfaaa;
    defparam time_cnt_2274_add_4_7.INIT1 = 16'hfaaa;
    defparam time_cnt_2274_add_4_7.INJECT1_0 = "NO";
    defparam time_cnt_2274_add_4_7.INJECT1_1 = "NO";
    CCU2D time_cnt_2274_add_4_5 (.A0(time_cnt[3]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(time_cnt[4]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24996), .COUT(n24997), .S0(n77[3]), .S1(n77[4]));   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274_add_4_5.INIT0 = 16'hfaaa;
    defparam time_cnt_2274_add_4_5.INIT1 = 16'hfaaa;
    defparam time_cnt_2274_add_4_5.INJECT1_0 = "NO";
    defparam time_cnt_2274_add_4_5.INJECT1_1 = "NO";
    CCU2D time_cnt_2274_add_4_3 (.A0(time_cnt[1]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(time_cnt[2]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24995), .COUT(n24996), .S0(n77[1]), .S1(n77[2]));   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274_add_4_3.INIT0 = 16'hfaaa;
    defparam time_cnt_2274_add_4_3.INIT1 = 16'hfaaa;
    defparam time_cnt_2274_add_4_3.INJECT1_0 = "NO";
    defparam time_cnt_2274_add_4_3.INJECT1_1 = "NO";
    CCU2D time_cnt_2274_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(time_cnt[0]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .COUT(n24995), .S1(n77[0]));   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274_add_4_1.INIT0 = 16'hF000;
    defparam time_cnt_2274_add_4_1.INIT1 = 16'h0555;
    defparam time_cnt_2274_add_4_1.INJECT1_0 = "NO";
    defparam time_cnt_2274_add_4_1.INJECT1_1 = "NO";
    FD1S3IX time_cnt_2274__i1 (.D(n77[1]), .CK(sys_clk_c), .CD(n2702), 
            .Q(time_cnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274__i1.GSR = "ENABLED";
    FD1S3IX time_cnt_2274__i2 (.D(n77[2]), .CK(sys_clk_c), .CD(n2702), 
            .Q(time_cnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274__i2.GSR = "ENABLED";
    FD1S3IX time_cnt_2274__i3 (.D(n77[3]), .CK(sys_clk_c), .CD(n2702), 
            .Q(time_cnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274__i3.GSR = "ENABLED";
    FD1S3IX time_cnt_2274__i4 (.D(n77[4]), .CK(sys_clk_c), .CD(n2702), 
            .Q(time_cnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274__i4.GSR = "ENABLED";
    FD1S3IX time_cnt_2274__i5 (.D(n77[5]), .CK(sys_clk_c), .CD(n2702), 
            .Q(time_cnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274__i5.GSR = "ENABLED";
    FD1S3IX time_cnt_2274__i6 (.D(n77[6]), .CK(sys_clk_c), .CD(n2702), 
            .Q(time_cnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274__i6.GSR = "ENABLED";
    FD1S3IX time_cnt_2274__i7 (.D(n77[7]), .CK(sys_clk_c), .CD(n2702), 
            .Q(time_cnt[7])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274__i7.GSR = "ENABLED";
    FD1S3IX time_cnt_2274__i8 (.D(n77[8]), .CK(sys_clk_c), .CD(n2702), 
            .Q(time_cnt[8])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274__i8.GSR = "ENABLED";
    FD1S3IX time_cnt_2274__i9 (.D(n77[9]), .CK(sys_clk_c), .CD(n2702), 
            .Q(time_cnt[9])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274__i9.GSR = "ENABLED";
    FD1S3IX time_cnt_2274__i10 (.D(n77[10]), .CK(sys_clk_c), .CD(n2702), 
            .Q(time_cnt[10])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274__i10.GSR = "ENABLED";
    FD1S3IX time_cnt_2274__i11 (.D(n77[11]), .CK(sys_clk_c), .CD(n2702), 
            .Q(time_cnt[11])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274__i11.GSR = "ENABLED";
    FD1S3IX time_cnt_2274__i12 (.D(n77[12]), .CK(sys_clk_c), .CD(n2702), 
            .Q(time_cnt[12])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274__i12.GSR = "ENABLED";
    FD1S3IX time_cnt_2274__i13 (.D(n77[13]), .CK(sys_clk_c), .CD(n2702), 
            .Q(time_cnt[13])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274__i13.GSR = "ENABLED";
    FD1S3IX time_cnt_2274__i14 (.D(n77[14]), .CK(sys_clk_c), .CD(n2702), 
            .Q(time_cnt[14])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274__i14.GSR = "ENABLED";
    FD1S3IX time_cnt_2274__i15 (.D(n77[15]), .CK(sys_clk_c), .CD(n2702), 
            .Q(time_cnt[15])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274__i15.GSR = "ENABLED";
    FD1S3IX time_cnt_2274__i16 (.D(n77[16]), .CK(sys_clk_c), .CD(n2702), 
            .Q(time_cnt[16])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274__i16.GSR = "ENABLED";
    FD1S3IX time_cnt_2274__i17 (.D(n77[17]), .CK(sys_clk_c), .CD(n2702), 
            .Q(time_cnt[17])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(73[15:30])
    defparam time_cnt_2274__i17.GSR = "ENABLED";
    LUT4 i1_4_lut (.A(BEEP_bus_c), .B(n29), .C(n34), .D(n30), .Z(piano_out_N_855)) /* synthesis lut_function=(A (B+(C+(D)))+!A !(B+(C+(D)))) */ ;
    defparam i1_4_lut.init = 16'haaa9;
    LUT4 i11_4_lut (.A(n4252[1]), .B(n4252[6]), .C(n4252[16]), .D(n4252[2]), 
         .Z(n29)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i11_4_lut.init = 16'hfffe;
    LUT4 i16_4_lut (.A(n31), .B(n4252[5]), .C(n28), .D(n4252[11]), .Z(n34)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i16_4_lut.init = 16'hfffe;
    LUT4 i12_4_lut (.A(n4252[10]), .B(n4252[4]), .C(n4252[8]), .D(n4252[13]), 
         .Z(n30)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i12_4_lut.init = 16'hfffe;
    LUT4 i13_4_lut (.A(n4252[14]), .B(n4252[17]), .C(n4252[15]), .D(n4252[9]), 
         .Z(n31)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i13_4_lut.init = 16'hfffe;
    LUT4 i10_4_lut (.A(n4252[12]), .B(n4252[7]), .C(n4252[0]), .D(n4252[3]), 
         .Z(n28)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i10_4_lut.init = 16'hfffe;
    LUT4 i722_2_lut (.A(n4271), .B(beep_en_reg), .Z(n2702)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(70[11] 74[5])
    defparam i722_2_lut.init = 16'hbbbb;
    CCU2D add_1237_19 (.A0(time_cnt[17]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n24976), .S0(n4252[17]), .S1(n4271));   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(70[14:32])
    defparam add_1237_19.INIT0 = 16'h5555;
    defparam add_1237_19.INIT1 = 16'h0000;
    defparam add_1237_19.INJECT1_0 = "NO";
    defparam add_1237_19.INJECT1_1 = "NO";
    CCU2D add_1237_17 (.A0(time_cnt[15]), .B0(time_end[15]), .C0(GND_net), 
          .D0(GND_net), .A1(time_cnt[16]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n24975), .COUT(n24976), .S0(n4252[15]), 
          .S1(n4252[16]));   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(70[14:32])
    defparam add_1237_17.INIT0 = 16'h5999;
    defparam add_1237_17.INIT1 = 16'h5555;
    defparam add_1237_17.INJECT1_0 = "NO";
    defparam add_1237_17.INJECT1_1 = "NO";
    CCU2D add_1237_15 (.A0(time_cnt[13]), .B0(time_end[13]), .C0(GND_net), 
          .D0(GND_net), .A1(time_cnt[14]), .B1(time_end[14]), .C1(GND_net), 
          .D1(GND_net), .CIN(n24974), .COUT(n24975), .S0(n4252[13]), 
          .S1(n4252[14]));   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(70[14:32])
    defparam add_1237_15.INIT0 = 16'h5999;
    defparam add_1237_15.INIT1 = 16'h5999;
    defparam add_1237_15.INJECT1_0 = "NO";
    defparam add_1237_15.INJECT1_1 = "NO";
    CCU2D add_1237_13 (.A0(time_cnt[11]), .B0(time_end[11]), .C0(GND_net), 
          .D0(GND_net), .A1(time_cnt[12]), .B1(time_end[12]), .C1(GND_net), 
          .D1(GND_net), .CIN(n24973), .COUT(n24974), .S0(n4252[11]), 
          .S1(n4252[12]));   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(70[14:32])
    defparam add_1237_13.INIT0 = 16'h5999;
    defparam add_1237_13.INIT1 = 16'h5999;
    defparam add_1237_13.INJECT1_0 = "NO";
    defparam add_1237_13.INJECT1_1 = "NO";
    CCU2D add_1237_11 (.A0(time_cnt[9]), .B0(time_end[9]), .C0(GND_net), 
          .D0(GND_net), .A1(time_cnt[10]), .B1(time_end[10]), .C1(GND_net), 
          .D1(GND_net), .CIN(n24972), .COUT(n24973), .S0(n4252[9]), 
          .S1(n4252[10]));   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(70[14:32])
    defparam add_1237_11.INIT0 = 16'h5999;
    defparam add_1237_11.INIT1 = 16'h5999;
    defparam add_1237_11.INJECT1_0 = "NO";
    defparam add_1237_11.INJECT1_1 = "NO";
    CCU2D add_1237_9 (.A0(time_cnt[7]), .B0(time_end[7]), .C0(GND_net), 
          .D0(GND_net), .A1(time_cnt[8]), .B1(time_end[8]), .C1(GND_net), 
          .D1(GND_net), .CIN(n24971), .COUT(n24972), .S0(n4252[7]), 
          .S1(n4252[8]));   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(70[14:32])
    defparam add_1237_9.INIT0 = 16'h5999;
    defparam add_1237_9.INIT1 = 16'h5999;
    defparam add_1237_9.INJECT1_0 = "NO";
    defparam add_1237_9.INJECT1_1 = "NO";
    CCU2D add_1237_7 (.A0(time_cnt[5]), .B0(time_end[5]), .C0(GND_net), 
          .D0(GND_net), .A1(time_cnt[6]), .B1(time_end[6]), .C1(GND_net), 
          .D1(GND_net), .CIN(n24970), .COUT(n24971), .S0(n4252[5]), 
          .S1(n4252[6]));   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(70[14:32])
    defparam add_1237_7.INIT0 = 16'h5999;
    defparam add_1237_7.INIT1 = 16'h5999;
    defparam add_1237_7.INJECT1_0 = "NO";
    defparam add_1237_7.INJECT1_1 = "NO";
    CCU2D add_1237_5 (.A0(time_cnt[3]), .B0(time_end[3]), .C0(GND_net), 
          .D0(GND_net), .A1(time_cnt[4]), .B1(time_end[4]), .C1(GND_net), 
          .D1(GND_net), .CIN(n24969), .COUT(n24970), .S0(n4252[3]), 
          .S1(n4252[4]));   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(70[14:32])
    defparam add_1237_5.INIT0 = 16'h5999;
    defparam add_1237_5.INIT1 = 16'h5999;
    defparam add_1237_5.INJECT1_0 = "NO";
    defparam add_1237_5.INJECT1_1 = "NO";
    CCU2D add_1237_3 (.A0(time_cnt[1]), .B0(time_end[1]), .C0(GND_net), 
          .D0(GND_net), .A1(time_cnt[2]), .B1(time_end[2]), .C1(GND_net), 
          .D1(GND_net), .CIN(n24968), .COUT(n24969), .S0(n4252[1]), 
          .S1(n4252[2]));   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(70[14:32])
    defparam add_1237_3.INIT0 = 16'h5999;
    defparam add_1237_3.INIT1 = 16'h5999;
    defparam add_1237_3.INJECT1_0 = "NO";
    defparam add_1237_3.INJECT1_1 = "NO";
    CCU2D add_1237_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(time_cnt[0]), .B1(time_end[0]), .C1(GND_net), .D1(GND_net), 
          .COUT(n24968), .S1(n4252[0]));   // f:/git/my/fpga/training_v2.0/code/beep/beep.v(70[14:32])
    defparam add_1237_1.INIT0 = 16'h0000;
    defparam add_1237_1.INIT1 = 16'h5999;
    defparam add_1237_1.INJECT1_0 = "NO";
    defparam add_1237_1.INJECT1_1 = "NO";
    
endmodule
